Shop OBEX P1 Docs P2 Docs Learn Events
Interesting eeprom programming quirk — Parallax Forums

Interesting eeprom programming quirk

jstjohnzjstjohnz Posts: 91
edited 2015-02-12 10:41 in Propeller 1
Just as I hit the "Load EEPROM" button I noticed that pin 8 (Vdd) of the EEPROM was bent out and had completely missed the socket. I waited for the "boing!" indicating programming failure but it never came. The EEPROM programmed and verified just fine with no connection to Vdd.

Apparently it was getting enough juice through the 4.7k pullups yo run....

Comments

  • BeanBean Posts: 8,129
    edited 2015-02-10 05:50
    It is more likely drawing power from the I/O pins when they are high through the protection diodes.

    Bean
  • RaymanRayman Posts: 14,652
    edited 2015-02-10 09:07
    That's funny. I wouldn't have thought it would work for writing at all. Maybe just reading wouldn't surprise me too much.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2015-02-10 09:12
    It probably works only if SCL is driven high, rather than being pulled high. Still, though, without the bypass cap connected, I'm surprised there's enough residual capacitance to hold things up between clock pulses.

    -Phil
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2015-02-10 09:45
    Don't forget that EEPROMs still need a programming voltage but unlike the old EPROMs this voltage is generated internally through a charge pump which also has sufficient capacitance on-chip. So yes, it probably is being powered directly through the I/O pin, across the forward junction to Vdd and when SCL is low then it is quite probable that on-chip capacitance for the input stage of the charge pump is sufficient to power the chip logic. More than likely this is working because SCL is being driven high by software rather than relying on the pullup and SCL only pulls low for a few microseconds each time when clocking.
  • cavelambcavelamb Posts: 720
    edited 2015-02-11 16:33
    Long long ago, when we were building early bed-of-nails type board testers I found that
    powered-down 8255s would hold configuration set-up from voltage from logic signals on the I/O pins.
    AND that was NMOS technology!

    So yes, it's probably being powered from the I/O pins.
  • Mark_TMark_T Posts: 1,981
    edited 2015-02-12 10:41
    Note that powered a CMOS chip this way, via I/O pin protection diodes, is the most likely way
    to send the chip into latch-up and fry it. CMOS latch up is due to parasitic SCR structures formed
    by the various p- and n-wells on the chip.

    Older CMOS designs were very sensitive, newer ones are usually optimised to be far less sensitive
    to latch-up (more current is needed to trigger it).

    Typical symptom of latch-up is the chip suddenly drawing lots of current and getting insanely hot. Can be cured
    by power cycling only, and you have to be quick to avoid permanent damage.
Sign In or Register to comment.