I have been keeping my eye on this new Altera line.
Hope the next version released for sale is the 10M25... That in the 144 pin QFP surface mount package with 101 I/O would make a great P1V that I could mount directly to my boards. No more having to rely on some 3rd party board maker.
I have been keeping my eye on this new Altera line.
Hope the next version released for sale is the 10M25... That in the 144 pin QFP surface mount package with 101 I/O would make a great P1V that I could mount directly to my boards. No more having to rely on some 3rd party board maker.
R.I.P P2
OpenSourced P1 internals => Self made P1V on low cost CPLD/FPGA => No P1 incomes for Parallax == R.I.P. P2
OpenSourced P1 internals => Self made P1V on low cost CPLD/FPGA => No P1 incomes for Parallax == R.I.P. P2
If you check the prices of those FPGA, they are still way above even a P1 in $/COG, so we are some years away from FPGA's being able to replace P1, - & the P2 will need even more costly FPGAs
Of course, if someone needs features not in a P1 (or P2) then a costly FPGA solution can become viable, but they were not a P1 customer anyway, as it could not do what they wanted.
I do see an opening for Parallax to offer a P1 and Max10 FPGA Board, where a moderate sized Max10 can augment the P1, with better peripherals.
This could give a good test vehicle for P2 peripheral field testing.
The main threat to P1 or P2, comes from parts cheaper than they are, not parts that cost more.
( eg "The STM32F070F6P6 with 32KB Flash and USB support in TSSOP20 package is priced from $0.57 for 10,000 units.")
The opening that I see for Parallax is if they could offer a preprogrammed Max10 with a full P1V with some basic enhancements (Port B, MUL, more Hub Ram, etc) in a (relatively) cheap module form. Something that would satisfy their commercial customers who really wanted a P1+ all these years. With the ability of the customer to add in custom logic as needed to optimize their design I think, for not price sensitive designs, they would have a good market. All depends on what the price breaks will be for that 10M25 that will fit a full 8 core P1V with some left over room to play with...
I would love to find a thru-hole mountable bare bones module like that.
P2 is going to have a weird market position. Cheap micro controllers hit it from the bottom and powerful ARM based designs hit it from the top.
The opening that I see for Parallax is if they could offer a preprogrammed Max10 with a full P1V with some basic enhancements (Port B, MUL, more Hub Ram, etc) in a (relatively) cheap module form. Something that would satisfy their commercial customers who really wanted a P1+ all these years. With the ability of the customer to add in custom logic as needed to optimize their design I think, for not price sensitive designs, they would have a good market. All depends on what the price breaks will be for that 10M25 that will fit a full 8 core P1V with some left over room to play with....
I'd largely agree, but think a P1 plus Max10 allows designers to use a smaller Max10.
eg P1 + 10M08 gives 12 cores, 8 Std and 4 enhanced.
Whack a RaspPi header down one edge & otherwise make it as small as possible.
MAX10 have a number of vertically compatible footprints, so there is scope to have a family of modiules, as that is an assembly line change.
@jmg
Standard 80MHz for starters. Verifying cogs and I/o at the moment, so far so good.
I'll bump the speed up later tonight. Maybe tomorrow I'lll try removing the video block.
Good link. Was that for 8 COGs ? - seems a Xilinx_LUT runs at 1404/COG, lower than Max10_LUT ~1850/COG
Video is about 70% the size of Two Timers, and ~50% of the ALU, so there is headroom there to trade off Vid for smarter Timers or smarter ALU etc.
Here's the initial source and programming files.
Basic configuration of 4 Cogs and 16K Hub.
32 I/O pins mapped to J5 connector (same layout as BeMicro CV board)
The 8 user leds are configured as cog leds like the other implementations.
Rom is unscrambled and Propeller Version is 10.
Initial tests were successful at clock speeds of 80,100,120,125, and 133 MHz.
More extensive testing is required to verify these speeds.
The Dual boot feature of Max10 is not usable when running P1.
The function appears to be hijacked by the ROM emulation.
The Dual boot feature of Max10 is not usable when running P1.
The function appears to be hijacked by the ROM emulation.
Interesting - I guess that keeps the die smaller, but adds a load-time delay, and makes direct Flash access to free up RAM more compelling.
Is it easy to update the ROM code without a Logic compile ?
Is it easy to update the ROM code without a Logic compile ?
A full compile is required to update the P1 ROM code.
Another change in Quartus 14.1 is the "Use Smart Compilation" option is now disabled (Grayed out).
Maybe this feature is only available now on the $ubscription Edition ?
Unfortunately I've been busy and so I haven't been around here for a while checking on what's up with the latest Prop stuff so it is cool to see all this progress. I certainly want to get back into it at some point and start playing again. Maybe when I see Tubular next and get the MAX10 board he's got for me I'll try to have another play - though I only have 14.0.1 Quartus II so I guess I'm in for some downloads.
I'm happy you were able to get 4 COGs going. When I was digging into the MAX 10M08 specs last year I had initially expected 3 COGs would be about the practical limit but you've managed to get 4 COGs in which is nice. No doubt once we start extending it with other logic/P1 enhancements, it could drop down a bit, but it's still a really good starting point.
Given there is quite a bit of user flash on this device I was hoping we would be able to also copy/boot the application from it without needing the addtional i2c ROM device. That would make a nice standalone system that is still potentially field upgradable.
Hi All
After quite a few experiments, it is possible to squeeze a 5th COG into the Max10 10M08.
If you sacrifice 1 counter or the video block from each cog you can fit an extra cog.
Optimistically I went for 6 with no counters and video but Quartus put an end to that idea.
Edit: BTW 3 cogs with 2 counters + video + 64IO also fits!
Hmm, I make that an impact of ~ 552LEs to add 32 io
17 :LE's per pin, a little higher than I would have guessed
That's right , 2 counters and 1 video block per cog.
I tend to not take the numbers that Quartus spits out too seriously.
In quite a few of my test builds Quartus has indicated no overflows in LE or memory bit usage.
These same builds have stopped with errors indicating design doesn't fit device.
The compile times can vary from 10 minutes to ~40 minutes depending on the combination.
The "Fitter" is the biggest contributor to these larger compile times.
My last successful build and test run in the Max10 was a 3 Cog 4 counters per cog No video and 64 IO combo.
All counters appear to be working correctly so far. All 4 counters support PortA and PortB.
Edit: Just a reminder that all the tested combinations have 16K Hub ram. (No combinations will support 32K)
Managed to successfully compile your Qar file this morning Brian, brave new world. Its taking around 8 minutes for a compile, which I'm happy enough with.
I was able to vary the cogs but haven't found where the hub memory amount is set just yet. Will try and load up the BeMicro Max10 later
Do you have Sizes and download/pgm times for
a) Flash program (Pgm CFMx) and
b) Skipping Flash PGM (download direct to FPGA config SRAM )
I've found numbers suggesting 20.8 sec for 10M08.CFM0 pgm.
Programming sof file to ram ~2 seconds
Program/Verify pof file to flash ~30 seconds
Not too bad really. (FYI. DE2-115 Cyclone IV is a lot slower,IIRC ~3 minutes to program/verify.)
Thanks - is the sof file pgm & verify, or just pgm ?
Do you need both of those downloads to get a working image, or is just the sof enough ?
The verify function is greyed out in Quartus Programmer for sof files.
The sof file is all you need to get the Max10 running a P1V image.
A pof file is generated from a sof file using "File >Convert Programming Files.." in Quartus and is only needed to program the image to flash.
Comments
I have been keeping my eye on this new Altera line.
Hope the next version released for sale is the 10M25... That in the 144 pin QFP surface mount package with 101 I/O would make a great P1V that I could mount directly to my boards. No more having to rely on some 3rd party board maker.
R.I.P P2
OpenSourced P1 internals => Self made P1V on low cost CPLD/FPGA => No P1 incomes for Parallax == R.I.P. P2
Of course, if someone needs features not in a P1 (or P2) then a costly FPGA solution can become viable, but they were not a P1 customer anyway, as it could not do what they wanted.
I do see an opening for Parallax to offer a P1 and Max10 FPGA Board, where a moderate sized Max10 can augment the P1, with better peripherals.
This could give a good test vehicle for P2 peripheral field testing.
The main threat to P1 or P2, comes from parts cheaper than they are, not parts that cost more.
( eg "The STM32F070F6P6 with 32KB Flash and USB support in TSSOP20 package is priced from $0.57 for 10,000 units.")
I would love to find a thru-hole mountable bare bones module like that.
P2 is going to have a weird market position. Cheap micro controllers hit it from the bottom and powerful ARM based designs hit it from the top.
eg P1 + 10M08 gives 12 cores, 8 Std and 4 enhanced.
Whack a RaspPi header down one edge & otherwise make it as small as possible.
MAX10 have a number of vertically compatible footprints, so there is scope to have a family of modiules, as that is an assembly line change.
BeMicro MAX10 board now running 4 cogs and 16K hub.
Did anyone put a conditional compile around the Video Block, to see how much logic that requires ?
Standard 80MHz for starters. Verifying cogs and I/o at the moment, so far so good.
I'll bump the speed up later tonight. Maybe tomorrow I'lll try removing the video block.
this post from overclocked was useful for understanding the breakdown of various blocks
http://forums.parallax.com/showthread.php/156842-Xilinx-port-started...?p=1284877&viewfull=1#post1284877
Video is about 70% the size of Two Timers, and ~50% of the ALU, so there is headroom there to trade off Vid for smarter Timers or smarter ALU etc.
Here's the initial source and programming files.
Basic configuration of 4 Cogs and 16K Hub.
32 I/O pins mapped to J5 connector (same layout as BeMicro CV board)
The 8 user leds are configured as cog leds like the other implementations.
Rom is unscrambled and Propeller Version is 10.
Initial tests were successful at clock speeds of 80,100,120,125, and 133 MHz.
More extensive testing is required to verify these speeds.
The Dual boot feature of Max10 is not usable when running P1.
The function appears to be hijacked by the ROM emulation.
Cheers
Brian
Is it easy to update the ROM code without a Logic compile ?
Another change in Quartus 14.1 is the "Use Smart Compilation" option is now disabled (Grayed out).
Maybe this feature is only available now on the $ubscription Edition ?
Unfortunately I've been busy and so I haven't been around here for a while checking on what's up with the latest Prop stuff so it is cool to see all this progress. I certainly want to get back into it at some point and start playing again. Maybe when I see Tubular next and get the MAX10 board he's got for me I'll try to have another play - though I only have 14.0.1 Quartus II so I guess I'm in for some downloads.
I'm happy you were able to get 4 COGs going. When I was digging into the MAX 10M08 specs last year I had initially expected 3 COGs would be about the practical limit but you've managed to get 4 COGs in which is nice. No doubt once we start extending it with other logic/P1 enhancements, it could drop down a bit, but it's still a really good starting point.
Given there is quite a bit of user flash on this device I was hoping we would be able to also copy/boot the application from it without needing the addtional i2c ROM device. That would make a nice standalone system that is still potentially field upgradable.
Cheers,
Roger.
After quite a few experiments, it is possible to squeeze a 5th COG into the Max10 10M08.
If you sacrifice 1 counter or the video block from each cog you can fit an extra cog.
Optimistically I went for 6 with no counters and video but Quartus put an end to that idea.
Edit: BTW 3 cogs with 2 counters + video + 64IO also fits!
For a 4 Cog + 2 Ctrs + Video + 32 IO
Total logic elements ; 7,447 / 8,064 ( 92 % ) Total combinational functions ; 6,783 / 8,064 ( 84 % ) Dedicated logic registers ; 2,888 / 8,064 ( 36 % ) Total registers ; 2888 Total memory bits ; 327,680 / 387,072 ( 85 % )and for a 3 Cog + 2 Ctrs + Video + 64 IOTotal logic elements ; 6,137 / 8,064 ( 76 % ) Total combinational functions ; 5,534 / 8,064 ( 69 % ) Dedicated logic registers ; 2,443 / 8,064 ( 30 % ) Total registers ; 2443 Total memory bits ; 311,296 / 387,072 ( 80 % )The latter figures I would expected to grow a bit as every IO pin is assigned to a real pin.
I haven't been able to run yet because I'm still on quartus 12.1, but I'll get to it soon
Better get Rogloh his max10 board
Hmm, I make that an impact of ~ 552LEs to add 32 io
17 :LE's per pin, a little higher than I would have guessed
That's right , 2 counters and 1 video block per cog.
I tend to not take the numbers that Quartus spits out too seriously.
In quite a few of my test builds Quartus has indicated no overflows in LE or memory bit usage.
These same builds have stopped with errors indicating design doesn't fit device.
The compile times can vary from 10 minutes to ~40 minutes depending on the combination.
The "Fitter" is the biggest contributor to these larger compile times.
My last successful build and test run in the Max10 was a 3 Cog 4 counters per cog No video and 64 IO combo.
All counters appear to be working correctly so far. All 4 counters support PortA and PortB.
Edit: Just a reminder that all the tested combinations have 16K Hub ram. (No combinations will support 32K)
I was able to vary the cogs but haven't found where the hub memory amount is set just yet. Will try and load up the BeMicro Max10 later
Thanks for putting that up.
Look in the hub_mem.v file to find these statements Simply 4 x 4K byte ram block = 16K byte Hub ram
Cheers
Brian
a) Flash program (Pgm CFMx) and
b) Skipping Flash PGM (download direct to FPGA config SRAM )
I've found numbers suggesting 20.8 sec for 10M08.CFM0 pgm.
Program/Verify pof file to flash ~30 seconds
Not too bad really. (FYI. DE2-115 Cyclone IV is a lot slower,IIRC ~3 minutes to program/verify.)
Do you need both of those downloads to get a working image, or is just the sof enough ?
The sof file is all you need to get the Max10 running a P1V image.
A pof file is generated from a sof file using "File >Convert Programming Files.." in Quartus and is only needed to program the image to flash.