Actually, what I was suggesting was a variant that was backwards-compatible with the P1. If you remove the video gen or change the Hub timing, it won't be backward compatible.
Oops. I meant to specify stripping out the vid gen hardware from the 8 additional cogs. Could there possibly be a need for 16 of them?
From what i recall, the hub could be made 1 clock instead of 2 giving 1:8 instead of 1:16 ie doubling hub speed.
I would be fairly confident the base clock could also be increased to maybe 120-160MHz with what Chip knows from P1 timing.
Even if the process is more expensive, the raw die cost is minor compared with all other costs including ROI, so internal Flash should be examined - solves security fuses and external flash. Presume a burdoned flash cost of 30cfor external flash. IIRC Chip said the raw die cost was ~$2.30 so even if internal flash increased this to 2.60 (and additional mask costs), surely this would remove a significant detracter for the prop. With the new contractors this should be easy to do without risks.
By careful design, the new features could be enabled by software meaning this could potentially replace the existing P1. Chip also now knows how to reduce hhub ram power usage so this might result in no more power for added features.
Even if the process is more expensive, the raw die cost is minor compared with all other costs including ROI, so internal Flash should be examined - solves security fuses and external flash. Presume a burdoned flash cost of 30cfor external flash. IIRC Chip said the raw die cost was ~$2.30 so even if internal flash increased this to 2.60 (and additional mask costs), surely this would remove a significant detracter for the prop. With the new contractors this should be easy to do without risks.
One P2 is done, I'm sure a retro-fit possible family of P1+ makes sense to investigate.
However, Flash is not without issues.
Flash does add to the cost as it needs more mask layers, and more testing.
(This may also lower the SRAM speed.)
4MBit flash is 18c/1000+, and whatever is placed on-die, will need external expansion choice.
Nuvoton has just released a part that has 2MB SPI flash inside the package,so that is another approach.
That allows a flash-less part to be offered, at lower price.
Nuvoton also have encryption on their SPI interface
Companies use OTP cells for security, & unique device IDs and those can be smaller and less masks than FLASH.
Parallax already plan OTP on P2, not sure if that is still their own design, or if they have moved to a fab-proven macro.
Then there is the clear experience and sign-off advantages of using the same process (non flash) proven in P2.
A P1+ in that process, that was backward compatible with P1, would need a regulator macro & a desire for a 100% pin clone may bump into the need of such included regulators to have decoupling caps.
Perhaps that can be bonded within the package ?
Well die stacking is certainly a possibility as many chips do that to incorporate flash, but would it be an option for Parallax to offer some chips with it if it's not produced in really high volumes? I'd hope so.
Comments
#2- more pins
#3- faster (1 clock instruction @ 80mhz or equivalent)
In fact, I'd be happy with just 1 and 2!
From what i recall, the hub could be made 1 clock instead of 2 giving 1:8 instead of 1:16 ie doubling hub speed.
I would be fairly confident the base clock could also be increased to maybe 120-160MHz with what Chip knows from P1 timing.
Even if the process is more expensive, the raw die cost is minor compared with all other costs including ROI, so internal Flash should be examined - solves security fuses and external flash. Presume a burdoned flash cost of 30cfor external flash. IIRC Chip said the raw die cost was ~$2.30 so even if internal flash increased this to 2.60 (and additional mask costs), surely this would remove a significant detracter for the prop. With the new contractors this should be easy to do without risks.
By careful design, the new features could be enabled by software meaning this could potentially replace the existing P1. Chip also now knows how to reduce hhub ram power usage so this might result in no more power for added features.
One P2 is done, I'm sure a retro-fit possible family of P1+ makes sense to investigate.
However, Flash is not without issues.
Flash does add to the cost as it needs more mask layers, and more testing.
(This may also lower the SRAM speed.)
4MBit flash is 18c/1000+, and whatever is placed on-die, will need external expansion choice.
Nuvoton has just released a part that has 2MB SPI flash inside the package,so that is another approach.
That allows a flash-less part to be offered, at lower price.
Nuvoton also have encryption on their SPI interface
Companies use OTP cells for security, & unique device IDs and those can be smaller and less masks than FLASH.
Parallax already plan OTP on P2, not sure if that is still their own design, or if they have moved to a fab-proven macro.
Then there is the clear experience and sign-off advantages of using the same process (non flash) proven in P2.
A P1+ in that process, that was backward compatible with P1, would need a regulator macro & a desire for a 100% pin clone may bump into the need of such included regulators to have decoupling caps.
Perhaps that can be bonded within the package ?