Hardware Heads: How do you clear the counters PLL dividers ?

Bean

I thought that setting PHSA to zero would clear the PLL dividers, but it doesn't seem to do that.

Does setting the counter mode clear them ? Or are they free-running and are not cleared by any operation ?

I'm trying to sync the counter outputs from two different cogs where the hardware counters are using the PLL modes.

Bean

Phil Pilgrim (PhiPi)

I don't know of any way to clear the PLL counters explicitly. It's probably easiest just to adjust the frequency of one until the edges coincide. Are both output frequencies the same, or is one a multiple of the other?

-Phil

kuroneko

The counter output syncs to the rising edge of the NCO feeding the PLL. This means you can easily sync the PLL output (across cogs) for dividers 1..16. I haven't seen a workable solution for dividers 32..128 yet (e.g. /128 can lock to any of the 8 rising NCO edges one of its cycles covers).

Bean

Thanks, Kuroneko. That makes sense with what I am seeing.

Bean

Phil Pilgrim (PhiPi)

Here's a program that works with the higher divide ratios:

CON

  _clkmode = xtal1 + pll16x                           
  _xinfreq = 5_000_000

  FRQ      = $0800_0000

VAR

  long  freq         

PUB start

  freq := FRQ
  cognew(@pll0, @freq)
  cognew(@pll1, @freq)

DAT

              org       0
pll0          mov       dira,#1
              mov       ctra,ctra0
              rdlong    frqa,par
:forever      jmp       #:forever

ctra0         long      %00010000 << 23 | 0

'_______________________________

              org       0
pll1          mov       dira,#6
              mov       ctra,ctra1
              rdlong    frqa,par
              mov       ctrb,ctrb1
              mov       time,cnt
              add       time,dt
              mov       frqb,#1
:lock_lp      waitcnt   time,dt
              mov       acc,phsb wz
              mov       phsb,#0
        if_z  jmp       #:locked
              shl       acc,#4
              add       frqa,acc
              sub       frqa,acc
              jmp       #:lock_lp

:locked       mov       outa,#4
:forever1     jmp       #:forever1

ctra1         long      %00010000 << 23 | 1
ctrb1         long      %10110 << 26 | 0 << 9 | 1
dt            long      $10000

time          res       1
acc           res       1

The output on P1 locks to the output on P0. Once locked, P2 raises.

-Phil