Prop2 Development Update
cgracey
Posts: 14,209
Merry Christmas, Everyone!
I hope you are all doing well and I thank you for sticking around through this protracted saga.
I reached a milestone yesterday. I finished the new schematic for the full-custom portion of the Prop2. Layout will begin soon. Once that is underway, I will be back on the Verilog side. There are four things that need developing in order to complete the chip:
1) Hub execution (Verilog, challenging)
2) Pipelined CORDIC in the hub (Verilog, pretty straightforward)
3) Smart pins (Verilog, not hard, but very open-ended)
4) ROM code (Prop2 assembly language, not hard)
I think that's all there is. Once that is all done, the whole chip can be assembled and we'll have it fabricated.
Meanwhile, I will be putting out new FPGA images as things progress.
Our new Cyclone V -A7 board is done, but not tested yet. We need to write some Prop1 code to make it work. It looks really nice, anyway. The one thing that that board will offer for Prop2 emulation that is unique from the other FPGA boards is a full 512KB hub RAM.
Thanks for reading! I hope to start getting FPGA updates out soon.
I hope you are all doing well and I thank you for sticking around through this protracted saga.
I reached a milestone yesterday. I finished the new schematic for the full-custom portion of the Prop2. Layout will begin soon. Once that is underway, I will be back on the Verilog side. There are four things that need developing in order to complete the chip:
1) Hub execution (Verilog, challenging)
2) Pipelined CORDIC in the hub (Verilog, pretty straightforward)
3) Smart pins (Verilog, not hard, but very open-ended)
4) ROM code (Prop2 assembly language, not hard)
I think that's all there is. Once that is all done, the whole chip can be assembled and we'll have it fabricated.
Meanwhile, I will be putting out new FPGA images as things progress.
Our new Cyclone V -A7 board is done, but not tested yet. We need to write some Prop1 code to make it work. It looks really nice, anyway. The one thing that that board will offer for Prop2 emulation that is unique from the other FPGA boards is a full 512KB hub RAM.
Thanks for reading! I hope to start getting FPGA updates out soon.
Comments
Thanks for the P2 update! Sounds like you're making great progress. Merry Christmas!!
David
Thanks for the update Chip. Sounds like all the ducks are lined up in a row
Bill
Product development is a long and winding road at best. Your efforts are greatly appreciated.
Meanwhile, I woke up this morning -- Christmas Day -- to a telephone call from the Taiwan Post Office saying that they would deliver my priority mail package from Parallax at noon. And at noon, I got my goodies (including a free surprise).
So it feels a bit Christmassy even if Taiwan just considers it a regular business day.
Thanks for the update Chip. Looking forward to new FPGA adventures in P2.
Paul
Thanks for the update, but do take some time off to spend with your family!
merry Christmas everyone
Merry Christmas Chip and family, Ken and family, all at Parallax, and all the forum members hope your day was as good as mine!
All the best!
Jim.
What is this about FPGA and a Parallax board? I'm eager to learn more when the time comes. I'd love to jump in with earlier development on the P2.
Oi! No talking of such. All that hub bandwidth and the thought of not being able to abuse it?! :P
One usage area I see is Motor control, and a trend in Asia is for 0.8mm packages for wave soldering.
You may be able to find a die-compatible (same package size as 128p 0.4mm) package, and plan the PAD placements to support bonding into a TQFP64 0.8mm as a 'future option' ?
We can certainly simulate and test a few iterations in this area in an fpga, to work out the minimum required at the pin end, and the minimum required at the cog end. That might help flush out what really matters
Thanks for the update
The smart pins could potentially do just about anything. I think to open this up on the FPGA so that people could write their own Verilog would be great. There are two commands in assembly language that will talk to these subsystems. One instruction configures pins via their DIR bit using clock/1 signaling, while the fastest software can change the DIR state is clock/2. The other instruction reads back serial messages coming from a pin's IN signal at clock/1. We may find a better way, of course.
It's a Cyclone V -A7 board that can be used for Prop1..3 development. That's its intended use, anyway. I don't know what we are going to sell it for, yet, but Altera gave us a good price on the -A7 device. If I recall, it has 150k LE's and enough RAM to support 512KB of hub memory. The board has 6 video DAC's, too, for fast analog out (2 x R-G-B).
2015 is looking like an action packed year!
Sometimes I am slow go grasp concepts. So some questions:
Besides 16 cogs, 512KB and HubExec we will have a subsystem on each pin, able to be configured via 'serial command'. Right?
Them Subsystems run independent of the cogs, sort of a programmable I/O pin - Smart Pin. Right?
So @Chip added another layer of parallelism between cogs and pins. Wonderful! Am I still Right?
This says to me that the core P2 can be finalized and tested while the SmartPin Subsystem still can get extended. Am I still Right?
Following them other posts there will be a lot of functionality possible in the SmartPins. Digital I/O, analog I/O, PWM and tons of other stuff not yet defined completely. What goes in will depend on die size, but yeah let the community here help to provide Verilog for @Chip to put in or not.
Good times ahead.
Like @Timothy D. Swieter I am waiting calmly for the Parallax FPGA Board (and the not yet announced seminar in Rocklin...)
Enjoy!
Mike
Here are some more infos about the FPGA Board:
http://www.parallax.com/news/2014-10-20/parallax-cyclone-v-fpga-development-board-programming-and-development-tool-propeller
Andy
I too can't wait to get the FPGA board. Let us know when they are available for purchase.
Bean
Also this teaser from Ken's twitter feed
https://twitter.com/ParallaxKen/status/542442366464831488/photo/1
Mike, you are right about the intention of smart pins. They perform asynchronous functions on their own, decoupling the cog from the pin activity. They can be independently developed, apart from the cogs.
Any ideas what kind of complexity would fit around the pins, or is it too early to say? Eg would a P1 counter per pin (or per pin pair) be around the right size?
I figure that we need at least that much logic to facilitate 32-bit adds and counts. Then, there's the serialization logic. You're right that the conduit is the IN, OUT, and DIR signals.
I'm not sure what this means for goertzel