Does the license allow commercial use?
steddyman
Posts: 91
Is the Propeller 1 verilog usable in a commercial setting?
For example if I wanted to sell an FPGA based board with a modified propeller code base that ran propeller code, could I do that?
Thanks
For example if I wanted to sell an FPGA based board with a modified propeller code base that ran propeller code, could I do that?
Thanks
Comments
Thanks
Please be sure to read here http://www.parallax.com/microcontrollers/propeller-1-open-source and check the terms of the license as seen here https://github.com/ZiCog/P8X32A_Emulation/blob/master/LICENSE
Basically my interpretation of this is:
1) You have to be prepared to give the source code of whatever you do to your customers if they ask.
2) You had better not expect that any code you add to that be closed. The GPL basically says that would be a derived work and you have to open it as well.
3) You had better not mix up anyone else's code that is covered by non-compatible licenses with the P8X32A code.
All in all GPL is an odd choice of license for a hardware design. But then it's kind of software I guess.
I am considering making my own single board computer. The Prop is just one option for the micro controller, but not the only one. Not sure where I am going with this yet anyway and may Open Source all of it (or may do nothing)
Potentially some chip fab could take that Verlilog and build and sell a billion devices from it. All they have to do is make that code, plus whatever else they added, available to anyone who wants it. Say a download on their web site. No probs.
Unlikely but a possibility. Say for example if said chip fab could churn out these clone Props for 50 cents each with free delivery.
Soft-Propeller, a DIP40 module with Programmable Device that if loaded with P1 code will come Soft-Propeller.
All open sourced hardware.
Preparing for launch end of 2014.
http://www.dailytech.com/IBM+Pays+GLOBALFOUNDRIES+15B+USD+to+Take+Fab+Business+Off+Its+Hands/article36743.htm
Interesting. Will see how Propeller respond to this.
If you want to keep your changes closed, contact us for a license. We would have a reasonable fee based on your volume. If you're going to use the FPGA in your product it's probably a low-volume effort with a higher fee, but if you want to make an ASIC then we should collaborate in more productive way depending on many variables in the engineering design, market potential, etc.
That's about all there is to it. When we said "open source" we meant it.
Ken Gracey
Herr Lukats! Many years, no communication. Happy to see you back in the mix - last time I was you was in Tallin or Helsinki in 1997.
Chip and I would love to hear more about what you're doing kgracey@parallax.com if you have a few minutes.
Ken Gracey
Helsinki was first time meeting, last was I think somewhere around Sacramento?
I just told my colleges here about the solder pot in the backyard, with BS2 going into it..:)
was a while ago.
[PLEASE SEE SUBSEQUENT POST FROM KEN AS IT OBSOLETES THIS ONE
Hey Antii,
Good memory, but it's really difficult to put the chronological events from almost 20 years ago in order.
Got your message and your plan is good, with our support and recognition. Will reply in a bit to your message. Points about the licensing:
- commercial products are okay provided the code is released (I think on our GitHub, need to figure this out fast) into the public
- closed source is fine too with an agreement to Parallax for license and payment
The product you made would be of interest to forum members so I hope you can share it openly.
Ken Gracey
steddyman,
Chip and I spoke and we're going to loosen the terms of our licensing. At the moment, if you release your design with attribution under the same open source license, you're complying with GPL 3.0. What we don't talk about is if you want to make a closed-source product with our Verilog code in it. At the moment, you are supposed to contact us for a license (and a royalty, presumably). However, we don't want to throw a wet blanket on any of the fun and want people and companies to develop with our core without concern for agreements (and the lawyers who want to be involved). After all, this kind of enthusiasm around the Propeller 1 brings direct benefits to Propeller 2. Heck, we don't even have the time to administer any silly royalty or licensing agreements. That's a big company thing and we adore innovation from the inventors and small shops that share our values.
So, whether or not you're open or closed, just go for it!
Same for you, Antii Lukats in Deutschland und auch von Estonia. Mach Spa
wau and yeah.
While the GPL clause and event the license/royalty was OK for me/us, I do welcome and agree that something else than GPL is wise. To be use with IP core licensing. Its a ever going discussion about software licenses applied to hardware.
Example company acme deigns a product that can be used with ip core under GPL
does this mean that source code that is used in bitstream that include ip under GPL are to be released ?
this is doable in the sense that acme releases all sources added and or modified
but if we if we read it such that all sources needed to compile bitstream that includes the GPL ip core have to be GPL as well? This is impossible as we all know as part of the vendor technology libraries are not GPL
there are plenty of other issues... hence yeah!
It is so refreshing to come across such a small yet open company in the microprocessor world. Would obviously attribute the cores to Parallax anyway.
Many thanks
Yo Antii,
What programmable part number does this use ? What Clock choices ?
Does this also have a USB connector / loader ?
-Tor
* DIP40, pin compatible, except that XI-XO are 2 more I/O
* microSD card, for boot images, virtual ram and eeprom images - this SD card interface is NOT accessible from propeller direct IO!
* si1143 IR gesture sensor, 2 IR LEDS, i2c propeller accessible
* 3.5mm audio video jack, audio out video out (mappable to prop IO) - we are not 100% sure about this, but currently its planned in
* 16 MByte flash
* RGB led, propeller accessible
* XC7Z010-CLG225
external clock is not required but can be synced to clock on XI pin if desired
as you see we did not include USB, reason: if there is usb connector, then it would be nice to CHOOSE power from USB, but then we have problem that any baseboard that accepts DIP40 propeller, does not want to see the 3.3V to come FROM the propeller, so it would make the power distribution and switching very complicated.
It would be trivial to have soft-prop USB, where the audio jack is replaced with microUSB
Wow, this is AMAZING Ken. The possibilities it opens up are astounding. The P1 simply will not do for my application and the P2 is a "long way out" so I looked at the P1V but the GPL issues turned me off from trying to use it.
Now if your FPGA board is flexible enough to be used in products (most boards are not) and not just educational tinkering you might have an amazing new product line here.
This sounds great, but will it still be 32KB HUB RAM? Have you considered adding an optimized MUL instruction like others have?
one full P8X32A (64KByte) takes 33.33% of RAM available
there is plenty of room for extensions..
the larger LED are the IR ones, the smaller red-green are visible ones, the PLCC4 is RGB led
We will use OZOM-Model A PCBs for prototype rev 0. for the propeller DIP, that module has most the features of the soft-propeller DIP, except 28 IO not 34, si1143 missing, audio-video plug missing, RGB led missing, but for early prototyping it is sufficient. The main functions are and ICs are the same.
I have about 12 boards at the moment, they not yet all reserved. So some could be owned before Christmas. I was hoping to have more hardware ready this year but well our SMT assembly guys wanted to start holidays early, so the next batches will be assembled in January only.
As of the soft-propeller DIP mod, I need to close the specs pretty soon, I want it to production ASAP...
SD access from P1: I can consider this, its not a real issue, my consideration was: it most likely not needed, and so the extra effort makes little sense, and secondly having the P1 access to SD would make the boot a little bit less safe, as there could be two processors trying to access the SD during the boot. But as the SD card can not be primary boot anyway, this issue can be solved also. Primary first boot is from SPI flash only, this is hardware restriction can not be changed.
order
As I said, we have some boards ready to ship this year, but not much, we will ship some to ozom early adopters, and the rest I guess I am forced to give away at 31C3 in Hamburg.
SD: it is PCB issue, for P1 access there would be either 2 balls per SD pin needed, or then use FPGA assisted access always, both are somewhat not ideal solutions. OK, the 2 ball per SD IO is OK, just a few mm more PCB traces