P1 on Xilinx FPGA

alukats

Hi,

I am trying to compile P1 code with Xilinx tools, and it seems dead-end, the synthesis tools just can not handle the verilog two dimensional wire statements.
I fixed some files do not produce errors, but at the moment it almost looks like it is easier to rewrite from scratch, by just looking a the original verilog code.

I just wonder where it would be the correct place to host the "converted" HDL code of the project.

Antti

pik33

There are some topics here about xilinx port, read them.
Maybe you simply have to set your compiler settings. For Altera it cannot compile until you set "System Verilog" as a verilog compiler.

alukats

yes, already got it, when selecting systemverilog for the toplevel file there are no errors. Now I only need to wrap it into Vivado IP Catalog compliant IP-XACT core..

Heater.

alukats,

Welcome to the forum.

Chip has indicated that he (Parallax) will take ownership of the github repo here : https://github.com/ZiCog/P8X32A_Emulation

That is basically still the code as originally released but with the tabs fixed up to ensure it always displays in editors the way Chip wrote it.

That repo has already been forked a bunch of times and I there is at least one pull request outstanding and probably more work in the other forks that might be finding their way up.

One approach would be to fork that repos and make you changes to your tree. Then issue a pull request. Eventually that will find it's way up to Parallax if they like it.

Chips has been a bit to busy to worry about github but I will send Parallax a request for ownership change ASAP.

alukats

Hi

yes i found the github pages also. the problem is that the original systemverilog code while it compiles ok, it can not be without modification converted into installable IP-XACT IP core the can be parametrized with Vivado. So at least some changes will be not ok for the mainstream repo.

http://hackaday.io/project/3443-open-source-hw-xilinx-zynq7000-system-on-module

This our target hardware i am porting P8X32A at the moment. While it would be possible to run the Prop core "standalone" it could of court interact with the ARM CortexA9 cores too. Or be used as peripheral accelerator.

pik33

I don't know Xilinx tools, but can't you wrap the P1V in external layer which will do its compatibility job?
Can't you use serial/parallel ports in your SoC to connect it to P1V?

I have a DE1-SOC board with Altera Cyclone V ARM/FPGA core. If I want to connect P1V with this ARM, I have to

- use a QSYS tool to make a system with this ARM
- add a parallel (or serial) port(s) to the system
- make a block symbol of the system
- use the graphics editor to connect the Propeller block with the ARM system block using this port.

I don't know how to make a P1V QSYS/Avalon compatible, but I don't have to. There are parallel/serial ports everywhere

---

I made a retromachine with P1V and all these things you can find on DE2-115 board. To do this I converted the P1V into a block symbol and then I connected my Verilog stuff to it in the graphic editor. So I think similar task can be done with Xilinx, too

The problem with original P1V and Xilinx is the top file is not Verilog. It is Altera AHDL. Then someone did the job and converted this to Verilog - there are topic about it and these converted files somewhere. So, maybe you can get this top file and then change it to make this compatible with your system.

Ariba

Hello alukats

There is already a Xilinx port of the Propeller 1 design for the Pipistrello board.
See this thread: http://forums.parallax.com/showthread.php/157004-Propeller-1-running-on-Pipistrello-(Xilinx-Spartan6-LX45)

Andy