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looking for a logic chip

dr hydradr hydra Posts: 212
edited 2014-11-24 02:25 in General Discussion
Is there a simple logic chip available that takes input from one pin...over two clocks/two inputs...and outputs the data on two seperate pins...an example 8 bit data could be convert to 16 bit data over two clocks...but using a latch so the output does not change until both input data is received...

Example... input pin A receives a 1 and then a 0...then outputs on pin B the 1 and outputs on pin C the 0...at the same time

Comments

  • TumblerTumbler Posts: 323
    edited 2014-11-17 09:05
    Take a look at this page: http://www.romanblack.com/shift1.htm
  • MrBi11MrBi11 Posts: 117
    edited 2014-11-17 09:13
    Maybe try two 8bit JK flipflops
  • kwinnkwinn Posts: 8,697
    edited 2014-11-17 10:49
    dr hydra wrote: »
    Is there a simple logic chip available that takes input from one pin...over two clocks/two inputs...and outputs the data on two seperate pins...an example 8 bit data could be convert to 16 bit data over two clocks...but using a latch so the output does not change until both input data is received...

    Example... input pin A receives a 1 and then a 0...then outputs on pin B the 1 and outputs on pin C the 0...at the same time

    If I am interpreting what you want correctly that can be done with a 74xx595 or other serial to parallel shift register.
  • jmgjmg Posts: 15,173
    edited 2014-11-17 12:22
    dr hydra wrote: »
    Is there a simple logic chip available that takes input from one pin...over two clocks/two inputs...and outputs the data on two seperate pins...an example 8 bit data could be convert to 16 bit data over two clocks...but using a latch so the output does not change until both input data is received...

    Example... input pin A receives a 1 and then a 0...then outputs on pin B the 1 and outputs on pin C the 0...at the same time

    Sure, a CPLD :)

    To do this on an Octal part, would need 8 in and 16 out, and no generic logic offers that.

    In a CPLD, you can buffer one 8 bit value, and then update all pins, needing 24 latches, 16 at pins and 8 buried.
    You can either use both clock edges, or add a phase flip flop, but a phase flip flop needs some reset pin to tell it if it is doing a Buried or Pin update.

    A 44 pin CPLD could even manage 8 in to 24 out, on a 3 edge design.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2014-11-17 14:46
    If you're not too fussy about the outputs appearing simultaneously, you could use a pair of 74HC374 8-bit D registers. Put an inverter between the clock inputs, so that one latches on the clock's rising edge; the other, on the falling edge. Present the same data to both chips' inputs: A data -> rising clock -> B data -> falling clock. If the A and B outputs have to update simultaneously, three of these chips, plus the inverter, would do the job.

    -Phil
  • dr hydradr hydra Posts: 212
    edited 2014-11-18 05:45
    Thank you for the help...I was hoping for a nice simple logic chip:)...CPLD looks like the best option...however...I would need it in a DIP...
  • jmgjmg Posts: 15,173
    edited 2014-11-23 00:48
    dr hydra wrote: »
    Thank you for the help...I was hoping for a nice simple logic chip:)...CPLD looks like the best option...however...I would need it in a DIP...

    DIP rather limits your choices, to devices like ATF2500 (DIP40) or ATF750 (DIP24) , and they are not cheap, or easy to pgm.

    If speed does not need to be super fast (ie a couple of us is ok, instead of sub 100ns) then you could use a simple small uC like a AT89LP52 - those are easier to PGM (ISP, 5V) and come under $1 in DIP40, moderate volumes.

    Is this being slaved to a Prop, or some other 8 bit micro ?
  • MJBMJB Posts: 1,235
    edited 2014-11-24 02:25
    dr hydra wrote: »
    Thank you for the help...I was hoping for a nice simple logic chip:)...CPLD looks like the best option...however...I would need it in a DIP...
    you know: 'for someone with a hammer everything looks like a nail'

    so if it is not for a high volume product just use a PROP, saves you the learning curve, tools etc. for CPLDs - unless you have it already

    8 in - 16 out
    2 COGs each waiting for it's rising/falling trigger to copy the 8 bit over to OUT
    the first one does a DIR input last one does a DIR Output

    a few lines in PASM

    you could even reuse the main props oscillator and load the ram from the main prop as well.

    so only a DIP 40 needed ;-)

    I did something similar for a legacy bus interface running a few 100 kHz.
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