Perfecting The ADC 3202 - Currently Its A Bit Jumpy

Mahonroy

Hey guys,
I am using the ADC 3202 chip (specifically the MCP3202-CI/SN) to read a 0-10v signal. I'm using a voltage divider to bring it down to a 0-5v signal so the ADC can read it properly.

I attached an image on how this is wired.

I am using the MCP3202 library by Chip Gracey.

It works... but the reading is a bit jumpy. I tried placing a 1uF capacitor at the input (shown in the attached schematic), and this did help, but its still pretty jumpy.

I also tried different values for the average function, and currently have it set to 100 (it averages 100 readings before using the "in" function).

What do you guys recommend to smooth this thing out?

Peter Jakacki

Mahonroy wrote: »

Hey guys,
I am using the ADC 3202 chip (specifically the MCP3202-CI/SN) to read a 0-10v signal. I'm using a voltage divider to bring it down to a 0-5v signal so the ADC can read it properly.

I attached an image on how this is wired.

I am using the MCP3202 library by Chip Gracey.

It works... but the reading is a bit jumpy. I tried placing a 1uF capacitor at the input (shown in the attached schematic), and this did help, but its still pretty jumpy.

I also tried different values for the average function, and currently have it set to 100 (it averages 100 readings before using the "in" function).

What do you guys recommend to smooth this thing out?

The ADC will only be as good as it's reference voltage which in the case of this device is tied to Vdd unfortunately. Now you have to ensure the Vdd is clean and filtered but you can also try sampling at a slower speed as well as averaging/filtering multiple samples except that I would include an acceptance window so that spurious readings outside this current window are not treated the same.

Sometimes it's easier and cheaper just to use a small micro with onboard ADC and reference etc. I've use a lot of Silabs parts for this as I can communicate easily over I2C and even Flash the chip in-circuit as well as let it do the filtering too.

So for now try filtering your Vdd and hopefully that will help a bit.

ksltd

Your circuit might be good for 2-6 bits of result - less than half of what the ADC can yield. To get a decent result, you need to do a lot more signal conditioning and seriously reconsider your Vref approach. You show no decoupling on the ADC and using the Vdd rail as the Vref is going to give you horrendous results.

The low-pass filter you show has a corner of around 15 Hz - so if you're sampling faster than 30 times per second, you're going to have aliasing problems and these will completely corrupt your results.

Your note doesn't say anything about what you're trying to accomplish. There are millions of documents online that explain how to match front-end filtering to sampling rate and how to provide reasonable real-world circuit protection while still obtaining reasonable SINAD. Generally speaking, it costs about US$10 to get 16 bits of resolution from a good quality sensor output and about $6 to obtain 12 bits (per channel).

There's just no way that a resistive divider and an electrolytic cap are going to give you 12 bits of data when the signal is from an external source.