BeMicro Max10 initial tests: 3 cogs wil fit.

jac_goudsmit

6581 posted a message about the BeMicro A9 which is probably out of range for most of us.

The BeMicro Max10 is going to be $30 (it's not available yet), so it's going to be in range of more developers.

Just for giggles, I downloaded the latest Quartus update which supports the Max10, and I created a new Revision in my project based on the 10M08DAF484C8G which is the chip on board the BeMicro Max10 and the other low-cost dev boards. The page says the 10M50 dev board will be available in December 2014 but I expect it to be much more expensive than the other ones.

The 10M08 FPGA only has 8064 LE's which is not even close to enough to fit an entire P1V. Even if I reduce the ROM size to 4092 (the absolute minimum to make the P1V boot), the memory won't fit inside the FPGA.

When I reduce the cog RAM to 16K (which won't work because the boot loader won't be able to verify the image), the fitter stops complaining about memory, but it still bombs with 220% LE's required.

When I reduced the number of cogs to 3, it compiled successfully (with warnings and with failed timing analyzer, but that's expected), even when I set the hub RAM back to 32K (ROM still set to 4K). Apparently the five removed blocks of cog RAM makes the memory fit as well as the video circuitry. It's using 7811 LE's (97%).

Here's a little overview; green marks the best of the category, red marks the worst of the category.



Board
DE0-Nano
DE2-115
BeMicro CV
BeMicro Max10
(theoretical)


Compilation time on 4-core i5
at 3.1GHz with 8GB RAM under
Windows 7 64 bits, for the 3-cog
configuration that fits the
BeMicro Max10 (NOTE: "your
mileage may vary")
2m12s
2m53s
10m09s
4m10s


Price
~$80
~$600
~$50
~$30


Features
Minimal
VGA, LCD,
7-segments...
MicroSD
Minimal


FPGA
Cyclone IV
(EP4CE22F17C6N)
~22K LE's
504Kbits RAM
Cyclone IV
(EP4CE115F29C7)
~114K LE's
3888Kbits RAM
Cyclone V
(5CEFA2F23C8N)
~9400 ALM's
1760Kbits RAM
Max 10
(10M08DAF484C8G)
~8K LE's
414Kbits RAM


Additional RAM on dev-board
32MB
128MB
128MB
8MB


Can run full P1V image
Must reduce ROM
size
Yes
Yes

Must reduce number
of cogs to 3, must
reduce ROM size



Utilization for 3-cog P1V
(based on my current Altera
branch).
Not a fair comparison criteria so
no winner/loser here.

5646 LE (25%)

5571 LE (5%)

3299 ALM's (35%)

7811 LE (97%)








Conclusion: The BeMicro Max10 may be a bit cheaper than the BeMicro CV and the DE0-Nano, but serious developers should ask themselves if the price difference is worth the difference in features and the difference in compilation speed.

Personally, I use the BeMicro CV but the long compilation times are starting to get seriously annoying, so I will probably get a DE0-Nano soon.

jmg

jac_goudsmit wrote: »

Apparently the five removed blocks of cog RAM makes the memory fit as well as the video circuitry. It's using 7811 LE's (97%).

Nice table, do you have % used figures for the other targets (it will be quite low for 3 COGS, but still a useful compare,
especially as the FPGAs structures differ now.)

jac_goudsmit wrote: »

Personally, I use the BeMicro CV but the long compilation times are starting to get seriously annoying, so I will probably get a DE0-Nano soon.

I wonder if Altera have any comments on this - it does seem strange to have to take such a large hit in speed.
I can imagine many customers would not tolerate that, so maybe some faster options are coming ?
I can understand a part that gets close to 100%, will take a lot longer to P&R than one < 75% full.
Could be interesting to check the compile speed of 2 COGS ?

jac_goudsmit

jmg wrote: »

Nice table, do you have % used figures for the other targets (it will be quite low for 3 COGS, but still a useful compare,
especially as the FPGAs structures differ now.)

I added the numbers in the last row. It's not a fair comparison because the LE's in each device work slightly different, and the P1V project could probably use some optimization. I think I actually turned some automatic optimization off on the BeMicroCV project to improve compilation time. And of course this is for 3 cogs, not 8. The BeMicro CV is almost full when you build a full P1V.

I wonder if Altera have any comments on this - it does seem strange to have to take such a large hit in speed.

I've been wondering about that too. Customers who figure out that they'll take a 2x hit in compilation time, are likely to choose the Cyclone IV over the Cyclone V, so I'm thinking the V is going to cost them a lot of money in the long run if/because they can't get their tools to work faster.

It's interesting that in the new Max10 line, they switched back from ALM's to LE's...

DISCLAIMER: I don't know enough about FPGA's to make this an authoritative answer; I'm just speculating based on the P1V project, and based on my own FPGA board which happens to be the BeMicro CV.

===Jac

jmg

jac_goudsmit wrote: »

I added the numbers in the last row. It's not a fair comparison because the LE's in each device work slightly different, and the P1V project could probably use some optimization. I think I actually turned some automatic optimization off on the BeMicroCV project to improve compilation time. And of course this is for 3 cogs, not 8. The BeMicro CV is almost full when you build a full P1V.

Thanks, it is because the cells are not quite the same in all cases, that the % and counts are useful to see.

Tubular

Thanks for that Jac

The BeMicro Max10's did exist for a while, and I successfully ordered one kit and one chip that are currently wending its way through some international freight logistics with other stuff. Hope to see them late this week.

Also digikey and mouser now both have stock of 3 variants of the 10m08 chips. They're not selling fast yet.

The U169 variant is a 11x11mm and only $15.41ea in 25 off qty, according to digikey. 4 layer OSHpark specs are a chance of working, at least with a slightly reduced pad size.

Cluso99

Nice table Jac.
I have been slowly reading some info on the Cyclone IV. It suggests that Quartus II is capable of partial compilation (ie doesn't recompile some parts that haven't changed). I wonder if it might be possible to have some of the P1V blocks not requiring recompilation. This might speed up the Cyclone V compilation. I am frustrated by the 3m for IV so 10m will really frustrate me. Looks like my BeMicroCV is not going to get a workout for a while yet.

jac_goudsmit

Cluso99 wrote: »

Nice table Jac.
I have been slowly reading some info on the Cyclone IV. It suggests that Quartus II is capable of partial compilation (ie doesn't recompile some parts that haven't changed). I wonder if it might be possible to have some of the P1V blocks not requiring recompilation. This might speed up the Cyclone V compilation. I am frustrated by the 3m for IV so 10m will really frustrate me. Looks like my BeMicroCV is not going to get a workout for a while yet.

I think smart compilation is turned on (at least for the BeMicroCV revision in my project). When you click the build button and nothing has changed to the source code, it won't actually build. But it's not actually the compilation that takes a lot of time, it's the fitter. That would imply that if we would use the Chip Planner, it might speed up compilation...

===Jac

Tubular

The BeMicro Max10 is back in stock at Arrow, with 40 units as of now
http://components.arrow.com/part/detail/NEG70145145S949927N1911

Tubular

Here's photos of the BeMicro Max10 module, with comparison to BeMicro CV and DE0-Nano.

I'm downloading the Altera software now (not just he programmer from P2) and hope to fire it up over the weekend.

Tubular

Here's some pics of Altera's Max10 evaluation board.

Compared with the arrow BeMicro Max10 offering, its a lot simpler (easier to follow whats going on). It uses the single supply rail version of the Max10. Apart from the fpga the only other ics are a tiny usb converter voltage reg and two quad opamps for scaling the 8 inputs from the Arduino headers. There's a single 50 MHz oscillator.

Edit: there's no onboard bit blaster, you need an external jtag cable