Dual Port RAM for COG RAM - not working

Cluso99

I am trying to get the COG RAM running as Dual Port RAM.
It seems to be instantiating this ram as dual clocked ram.

Anyway, it is not working and I am at a loss to determine where the problem lies.
My code is the original base code for the DE0-Nano with the following changes
* Chip's fixes
* dig.v changed to only generate3 cogs
* cog.v changed to not generate vga for any cogs
* cog.v now uses cog_dpram.v
* cog_dpram.v now included

Are there any top level changes required to specify dual port ram be used ???

pik33

What are you doing then with the second RAM port and the data you get from it? Do you write anything with this second port? If it is only declared and not used, the Quartus will simply optimize it, throwing the second port out.

Cluso99

Currently i am reading the destination using the second port. Once I get this to work i can commbine the S and D reads into a single clock which will make a 3clock instructions. Then i want to combine R and I. Then i can pipeline two instructionsto give 2 clock instructions.

Bill Henning

2 clock instructions would be REALLY NICE.

Cluso99

Been reading. Seems I have to use the mega function wizzard to create the dpram function. I will try this over the w/e.

Cluso99

So far, I have still failed to get the Dual Port RAM working.
Does anyone have a dual port working example of anything that I can use to test?

ozpropdev

Ray,
Have a look at rogloh's post, he has dual-port ram going in his code.

Cluso99

Thanks Brian. I missed how Roger did that - must have been in a hurry when I read that post because I didn't even look at the block diagram.
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