Altera MAX 10 early info
jmg
Posts: 15,173
Addit (via Chinese, but the price of Eval kit is what matters 
["Altera is not just the launch of MAX 10 chips, including [B]starting $30 evaluation kit[/B], software, design examples, training and related documentation, which for engineers They save a lot of time."]
From another thread : (some info added)
Document found above is called MAX10_Family_Overview.pptx (2.72 MB)
I'll try to attach just pages 9-12 pdf as a smaller package/resource summary.
The 3x3mm and 4x4mm packages give a hint to the prices, as that shows the die-size.
The Chinese link above says
["MAX power range of 10 to 100 mW (standby) ~ 1 W (operating at 200 MHz), the price is very low."]
A 2048 LUT Lattice device with 27io, is ~ $4 in low volumes.
The small packages at 27io and 56io seem to target the present smaller CPLDs, for another hint at price.
The P1V device could be
10M25 25,000 LUT 756kb (94.5kB) RAM, 256kb (32kB) FLASH, 61 18x18 Mults
Also has ADC (12b?) and a Dual plane config, with SDR SDRAM, SRAM, DDR3, DDR2, or LPDDR2
Sizes choices are 2/4/8/16/25/40/50 K LUT
- and it will be interesting to see how many COGS can fit into a 4x4mm 8000 LUT part.
Maybe the "will be officially in October 1" is the formal release date ?
["Altera is not just the launch of MAX 10 chips, including [B]starting $30 evaluation kit[/B], software, design examples, training and related documentation, which for engineers They save a lot of time."]
From another thread : (some info added)
Data about Altera MAX 10 FPGA (using 55nm Flash process):
- Integrated 55 nm dual Flash (dual boot + user flash)
- Integrated ADC, DSP, DDR interface, Oscilator, PLLs, LDOs
- from 2K to 50K Logic Elements (P1V uses around 15K LE in Cyclone IV/V).
- Block RAM from 108Kb to 1,638 Kb
- Standby power 10mW - 100mW. Max operational power: 1W
- Single 3v3 => 144-EQFP package (16x16mm 0.4mm, 101 io) for all variants, plus some BGA.for 112,130io
- Dual Vcc => All BGA packages, examples of
Smallest BGA 3x3mm 0.4mm 27io, 2000 LE only (108kb RAM, 96kb F)
Next Smallest BGA 4x4mm 0.4mm 56io, 8000 LE only (378kb RAM, 256kb F)
Widest BGA 17x17mm 1mm 178 io, 4000-50,000 LE
25,000 LE part, has (756kb (94.5kB) RAM, 256kb (32kB) F)
50,000 LE part, has (1638kb (204.75kB) RAM, 512kb (64kB) Flash)
- Price : unknown yet
First images: http://www.eeworld.com.cn/FPGA/2014/0924/article_3505.html
Leaked confidential document: search google for its own name "Altera 10M08"
Document found above is called MAX10_Family_Overview.pptx (2.72 MB)
I'll try to attach just pages 9-12 pdf as a smaller package/resource summary.
The 3x3mm and 4x4mm packages give a hint to the prices, as that shows the die-size.
The Chinese link above says
["MAX power range of 10 to 100 mW (standby) ~ 1 W (operating at 200 MHz), the price is very low."]
A 2048 LUT Lattice device with 27io, is ~ $4 in low volumes.
The small packages at 27io and 56io seem to target the present smaller CPLDs, for another hint at price.
The P1V device could be
10M25 25,000 LUT 756kb (94.5kB) RAM, 256kb (32kB) FLASH, 61 18x18 Mults
Also has ADC (12b?) and a Dual plane config, with SDR SDRAM, SRAM, DDR3, DDR2, or LPDDR2
Sizes choices are 2/4/8/16/25/40/50 K LUT
- and it will be interesting to see how many COGS can fit into a 4x4mm 8000 LUT part.
Maybe the "will be officially in October 1" is the formal release date ?
Comments
The other thing to like is the fact the whole family will be available in a 144 "EQFP"
Any ideas what TSD might stand for (in same column as ADCs) ?
I really hope Parallax will be able to capitalize on these
Seems to always be one only (or none on smallest with no ADC / single code image ).
I am sure they will.
The $30 price mentioned, hopefully is for the 50k LE
I'm really looking forward to seeing the first development boards available with this family on them.
It appears to only have 61k x 9 memory in the 16k LE version, while the larger one gets 84k x 9 which would allow the full range of hub RAM to be accessed and 4kB to spare (you could then map in the bootloader/SPIN interpreter at will and potentially reuse the top 4kB). Or perhaps some of the flash may be mappable as hub ROM too. We'll have to see how that all works.
These are small parts on the FPGA yardstick, so I would expect all variants to be in the base web-tools.
It would be nice to know exactly which device is used in the $30 Eval system.
If Cyclone IV LE usage is any reasonable estimate for this new MAX 10 FPGA family you could probably still squeeze about 2 or 3 COGs into that size with a bit of logic free, 4 probably wouldn't fit unfortunately. Could be very useful though for smaller applications that don't need so many COGs (eg, one COG running LMM or native from a larger COGRAM and a couple of other COGs doing real time stuff).
Looking at the tiny packages available you still can make a 56 I/O pin gizmo out of the little 4x4mm2 8000 LE variant, and that'd be a fun little toy to play with. Given you now don't need the typical extra FPGA support chips and only a single supply it would be a pretty flexible device you could turn into lots of things. Add an internal USB interface in the FPGA and it could be a hit.
So who wants to be first to build a tiny breakout for the WLSCP chip once they become available? Just need to find a nice rugged/cheap high density connector to match the size of the chip and to bring out a decent number of the 56 I/O pins. Once that happens Tindie may get a whole lot more products soon. Forget Arduino, let's just turn this thing into an miniaturized platform using the P1V. An Attoino. Ok, I just claimed that name.
Happy days ahead.
For example imagine something like this but even smaller, with a 3 COG P1V and 56 I/O pins, xtal, voltage reg, USB. https://www.tindie.com/products/TinyCircuits/tinyduino-starter-kit/ Tubular, you'd be right into that wouldn't you?
Thanks.
Altera must also be planning a 50k LE Eval, so there should (eventually) be two Eval order codes.
It may be the 8000 part is first bug-free enough, or they wanted to hit a $30 price point.
Latice started with a mid-size part, and then flipped to the largest MachXO2 on their Eval board
Is that an official challenge : )
I guess there's nothing to stop us getting some small universal breakouts made up while we wait, so we can hit the ground running. It would be easy then to adapt to some final form factor.
The "easy pcb" version of the chip also sounds interesting. Nice of them to think about making our lives easier
Neat thing on tindie. I started on a prop 1 design that fitted a 20mm dual coin cell holder (the prop board being one "coin", with one real coin cell in series with it, so you just had to close the circuit to enable the prop. Getting connections out is the hard bit, but some battery holders have a 'spillway' for want of a better term
(10M50 are coming " Available for order in December 2014 ")
This link shows 4 Eval kits
http://www.altera.com/devices/fpga/max-10/design-tools/max-10-design-tools.html#devkits
$30 10M08DAF484C8G BeMicro, with 8 MB SDRAM *
$35 10M08U169C8G Macnica with SDRAM
$49.95 Altera EK-10M08E144ES/P ( no SDRAM ?)
$?? 10M50DAF484C6G 512Mb x 16 DDR3 memory 1Gb QSPI - coming
* The BeMicro seems to be the only cheap board with inbuilt USB-pgm, the other two have JTAG headers.
The still-coming 10M50DAF484C6G board shows 2 USB pathways, looks like a FT2232H, one for ISP and one for UART use.
The prices shown a re
10M08SAU169C8GES 1: $19.26,
cheaper than the
10M08SAE144C8GES 1: $25.56
or
10M08DAF484C8GES 1: $35.73
No prices showing on the 10M50 yet.
Data says "The VCO frequency is a critical parameter that must be between 600 and 1,300 MHz to ensure proper operation of the PLL. The Quartus II software automatically sets the VCO frequency within the recommended range based on the clock output and phase shift requirements in your design."