OpenSpin-V

Willy Ekerslyke · 2014-09-19 14:54

The attached is a bit of a hack to OpenSpin so that those wishing to try out Cluso's AUGDS/S, rogloh's PUSH/POP/LOAD/STORE and my MUL/S instructions can do so without having to deal with the instruction's binary.

I have to confess that due to lack of time I've not actually run any generated code on a P1V - relying instead on inspection of the output to validate the encoding.

There's a readme in the archive and a .spin file that simply lists the new PASM instructions. Obviously this is the full OpenSpin compiler so unless I've really messed up it will handle all existing spin/PASM code too.

Ultimately this will need to become a github fork of the official OpenSpin but there seems little point at the moment while we're just experimenting.

I'll try to keep this up to date with further additions/changes the P1V instruction set but the code is there for others to chip in as well.

UPDATE v2: Added support for rogloh's PUSH POP RETX JMPX CALLX. Also added a 'lst' directive to control printing of the instruction binary.

Cluso99 · 2014-09-19 17:52

Tks willy. Won't get much time to test for 2 weeks as have daughter husband and twins visiting from s. Korea

rogloh · 2014-09-19 19:01

Good stuff Willy. I just now took a brief look and see you've included my HUB based PUSH & POP and LOAD/STORE change so far. I didn't see the COGRAM PUSH/POP/CALLX/RETX as well in there. Those all use the ONES instruction opcode 000111. That would be nice to play with too if you were planning to include it at some point.

Cheers,
Roger.

Willy Ekerslyke · 2014-09-20 00:05

Roger

Not sure how I missed those

I'll see what I can do over the next couple of days.

pik33 · 2014-09-20 00:35

Is it possible to make a definition file like

[ports]

outc $1ed
inc  $1ee
dirc $1ef

[instructions]


div  011001 000i 1111 ddddddddd sssssssss
atan 111111 1111 0011 ddddddddd sssssssss

to make adding new opcodes easier at user level?

Willy Ekerslyke · 2014-09-20 01:21

Pik33,

Yes it's possible but not without rewriting the entire assembler part of OpenSpin. The current assembler is very much tied to the real P1 instruction set and also shares features with the Spin compiler.

Perhaps adding a macro capability would go some way to giving user-level flexibility - I'll give it some thought but make no promises

ozpropdev · 2014-09-20 04:09

pik33
Using a CON block to define your port definitions solves part of your request.

CON
    #$1ed,outc,inc,dirc

I'm currently working on a custom assembler that allows for user defined instruction coding but it's very much a
work in progress. My radical P1V experiment requires it for 10bit source & destination addressing. I need
it to tweak the booter and allow the spin interpreter to take advantage of double cog ram.
This will assist in moving the SPR's from $1F0 to $3E0 too.

Cluso99 · 2014-09-20 14:41

I would recommend keeping the SPRs from $1F0..$1FF as there are a number of quirks that use these fixed locations. Even the verilog uses a quirk to clear down these registers at cog load time.

ozpropdev · 2014-09-20 19:34

Cluso99 wrote: »

I would recommend keeping the SPRs from $1F0..$1FF as there are a number of quirks that use these fixed locations. Even the verilog uses a quirk to clear down these registers at cog load time.

Ray
I believe I've already sorted the SPR zeroing issue with the following change to cog_alu.v

		: run || ~&p[8:4]		? bus_q
changes to
		: run || ~&p[9:5]		? bus_q

In order to increase the number of available SPR's for more ports,cpunters.etc I have to move them to $3E0 to $3FF (32 rges instead of 16)
This was also necessary to allow the spin interpreter to be expanded without overlapping the SPR address space. Many more changes have been made to accommodate
the 10 bit addressing. It's a bit of departure from the "standard P1".

Cheers
Brian

Willy Ekerslyke · 2014-09-21 10:42

Updated first post with new version (v2).

OpenSpin-V

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