Verilog Challenge
rjo__
Posts: 2,114
There is a group of us here that would freely admit that if Parallax hadn't released the P1 Verilog, we wouldn't have been very interested in Verilog. But Parallax did and here we are... BUT>there comes the rub... there is a long way between interest and facility.
If you have the facility... please turn the PUSH/POP variant into a speed demon... it currently doesn't save clocks in the application area of my choice(imaging)... so fix it.
If that challenge isn't your cup of tea(glass of beer in Australia)... then how about re-incarnating Chips REPS instruction in such a way that the only clocks use are for the code inside
of the loop and not the loop itself.
Not simple... but if it were simple... it wouldn't be a challenge ... would It?
Feel free to publish your results in Polish.
Rich
If you have the facility... please turn the PUSH/POP variant into a speed demon... it currently doesn't save clocks in the application area of my choice(imaging)... so fix it.
If that challenge isn't your cup of tea(glass of beer in Australia)... then how about re-incarnating Chips REPS instruction in such a way that the only clocks use are for the code inside
of the loop and not the loop itself.
Not simple... but if it were simple... it wouldn't be a challenge ... would It?
Feel free to publish your results in Polish.
Rich