Run P1v under emulation?

David Betz

Is there a way to run the P1 Verilog code in an emulation mode that will give waveform traces? I have a sneaking suspician that if I start modifying the code I'll rapidly break something and it won't be easy to debug on the FPGA.

jac_goudsmit

David Betz wrote: »

Is there a way to run the P1 Verilog code in an emulation mode that will give waveform traces? I have a sneaking suspician that if I start modifying the code I'll rapidly break something and it won't be easy to debug on the FPGA.

Quartus has a simulator and a logic analyzer built in but I don't know how it works (yet). I'm going to have to look into it though, because as you say, testing on the FPGA is not easy, especially if every compilation takes 10-15 minutes (reminds me of the "Good Ole Days" of my 80386 PC with a whopping 8MB of memory an 70MB of hard disk, which took 20 minutes to compile hello.cpp in Visual C++ 1.0 in 1993). I'm trying to reorganize the hub memory module a little bit to eliminate the copy-paste code and I feel as if I've been waiting for the compiler the entire weekend without hardly making any progress...

===Jac

Seairth

I've got the two ADHL files converted to Verilog (for Altera chips), which I will post shortly as soon as I verify that they are working (for the DE0-Nano and BEMicro CV). I'll try it out with ModelSim and let you know what I find.

Cluso99

If you put my VGA mod in, your compile times reduce by quite a bit.
My VGA is only compiled for cog 0.
Also, simply reducing the cogs to say 4 also reduces compile times. (just change the i++ statement)
My times are ~3.5 minutes with 4 cogs, vga on 0, 4KB cogs, 48KB hub, Quartus14 Windows8.1 i3-3217U (1.8GHz dual core) on Acer Aspire E1-570 laptop.

I too would be very interested to see how to get a timing diagram from QUartus. There is also a $display?? statement that should execute during compile but I haven't been able to get this to work.

ozpropdev

On the "BIG P2" we had the fabulous SETTRACE facility that allowed us to capture flag state, PC and other important stuff.
Maybe a variant of this could be implemented on P1V that fills a chunk of the available external RAM on our boards.
With this type of data we can get at the nuts and bolts of our work/changes.
Even a single-step function would assist here too....

Todd Marshall

jac_goudsmit wrote: »

Quartus has a simulator and a logic analyzer built in but I don't know how it works (yet). I'm going to have to look into it though, because as you say, testing on the FPGA is not easy, especially if every compilation takes 10-15 minutes (reminds me of the "Good Ole Days" of my 80386 PC with a whopping 8MB of memory an 70MB of hard disk, which took 20 minutes to compile hello.cpp in Visual C++ 1.0 in 1993). I'm trying to reorganize the hub memory module a little bit to eliminate the copy-paste code and I feel as if I've been waiting for the compiler the entire weekend without hardly making any progress...

===Jac

Try one day turnaround with punched cards. "Desk Checking" was a necessary skill.

Willy Ekerslyke

ModelSim is very strict with Verilog syntax. It doesn't like a reg or wire to be referenced in the code before it's declared and that sort of thing is rife in the P1V code (making it easier to follow IMHO).

ModeSim also barfs on things like an extraneous trailing comma whereas Quartus will just suck it up.

Assuming we can get past these (and probably other) issues there is then the problem of creating a stimulus file that will mimic the incoming serial programming stream. Perhaps, instead, we'd need to preload the Cog RAM with a $readmemh and modify the boot code to suit.

I seem to recall Chip saying that he doesn't use simulation - relying on analysis of output instead. No wonder really

Seairth

Willy Ekerslyke wrote: »

ModelSim is very strict with Verilog syntax. It doesn't like a reg or wire to be referenced in the code before it's declared and that sort of thing is rife in the P1V code (making it easier to follow IMHO).

ModeSim also barfs on things like an extraneous trailing comma whereas Quartus will just suck it up.

Assuming we can get past these (and probably other) issues there is then the problem of creating a stimulus file that will mimic the incoming serial programming stream. Perhaps, instead, we'd need to preload the Cog RAM with a $readmemh and modify the boot code to suit.

I seem to recall Chip saying that he doesn't use simulation - relying on analysis of output instead. No wonder really

Ugh. I see what you mean. I'm getting "errors" left and right. And as soon as I fix one, three more pop up. At this rate, the current code would require quite a number of tweaks before ModelSim will understand it. I didn't realize it was that finicky.