Tired after lots of Quartus

ozpropdev

LOL I just realized if you say that quickly with an Aussie accent it sounds like I'm talking about something else!

Riding the new roller-coaster called "Quartus" and felling terror, nausea and the thrills of FPGA/Verilog I share the following observations.

Many thanks to Parallax for allowing us to look under the "hood" of the Propeller. It has given me a whole new appreciation for the device.
Not that I fully understand it all yet but I understand it enough to get addicted to this whole FPGA experimentation universe.
With my new found (limited) knowledge of Verilog I feel quite "dizzy" thinking about the code Chip was working with in the "BIG" P2 with
it's pipelines,indirect registers,pointers,multi-tasking etc.etc. I know have a new appreaciation for the "battle" Chip has had with the
whole design process and dealing with large cycle times in between compile times and testing.
I now understand it when Chip uses the term "Virtually for free" in regard to some instructions and realize the complexity of others.
To sum up, WOW! what a ride we are all on.

Hats off to Chip for your great work. Thanks for sharing. Much appreaciated

Cheers
Brian

Cluso99

I echo your thoughts and observations.

It's easy to see how simple some things are, and how complex others are. I am still trying to get AUGDS working - well the basics working so I can verify it.

Many thanks to Chip and Parallax for the brave step in sharing this with the world. I am truly indebted to you.
Ray

Peter Jakacki

I haven't been able to touch this stuff in the past week or two so I can't say I'm "tired after lots of Quartus" (hey, just what are you saying Brian). But as an Aussie and fellow forumista I'd like to chip in with an acknowledgement of the work that Chip has done and is doing and has made freely available.

We really appreciate it mate! Gudonya! You're a top sport.

Peter

pik33

Cluso99 wrote: »

I echo your thoughts and observations.

It's easy to see how simple some things are, and how complex others are. I am still trying to get AUGDS working - well the basics working so I can verify it.

Ray

I tried to execute directly from inb. The first try failed - the Propeller Tool can't detect the Propeller chip. What looked to be simple (stop the program counter if it reaches inb) is not as simple as it looked. I don't know why this one if added destroyed the ability to detect the Propeller. and it needs some investigation. But now I am tired too. I overdosed the Quartus with some propeller tool and BST added.

Ale

My programming since 2012 or so is practically just verilog. I target either the Lattice MachXO2 or the Cyclone V, I also have some Xilinx parts, but I really have to feel low to do that to myself, I mean go through WebISE, for the old Spartan 2.
But what I wanted to say is that I just use the simulator, icarus verilog. It allows for fast development. Of course that it is not like compiling for a target because you can make many mistakes that result in non-synthesize-able code. `default_nettype none helps but does not solve the problems . You can also use ModelSIM provided by Altera, I haven't invested any time on it but I am sure you can get even better results. One way of avoiding non-working designs is to from time to time to compile with a real compiler, I mean for instance with quartus, my choice is synplify (yes, it is a 'n' ).
Chip gave us something great but my attention went away as I heard about RISC-V . I made my own version of the propeller a few months ago, I see we did things a bit different, Chip's work is a work of art, I like mine as an evolution of many tests I made. I find the cogs great for what they are: configurable software peripherals, I mean they are just great. One of the issues to address is the low speed i/o. 64 pins is a way, but an external memory controller (not a soft-controller) for the HUB would be just great.
I just wanted to say, that there are other ways to develop the P1V beyond what Chip gave us and not necessarily using quartus.

Have fun,

Ale

jazzed

Quartus fatigue!

Been there, had that. Having to wait for tools is horribly unproductive.

Ale wrote: »

But what I wanted to say is that I just use the simulator, icarus verilog. It allows for fast development. Of course that it is not like compiling for a target because you can make many mistakes that result in non-synthesize-able code.

I've been through that too. I once hacked a project that worked perfectly using Icarus verilog, but wouldn't synthesize with any tool. At the time I had no idea why. Since the P1V thing came out, I sat down and read more about verilog. The reason my code wouldn't synthesize then became very clear (invalid verilog!). So obviously Icarus has limits, and they should be made clearer somehow.

Icarus is a great tool for learning what the verilog does without waiting forever for vendor tools.

cgracey

Well, my Quartus work has been interrupted to get our pin schematic into proper shape for the ONC18 process we'll be using. It's a diversion I'd been putting off for some time.

Ale

Regarding what you cannot synthesize most books warn about it, but use such constructs without a second thought, sad. That is why I use synplify to check.

I mean this is wrong but can be used in icarus with not very nice results...

assign a = some_signal;
wire [3:0] quad;
assign a = some_other_signal;

you don't event get a warning for that ...And uninitialized registers are also a source of problems, but that can be helped with an initial directive... sometimes I forget them too

And the errors you get, I mean how the code behaves can be quite bluffing

Ale

Hei Chip, did we ( I ) miss something ?, do we get a new prop ?

jmg

cgracey wrote: »

Well, my Quartus work has been interrupted to get our pin schematic into proper shape for the ONC18 process we'll be using. It's a diversion I'd been putting off for some time.

Does that mean there is a small test run of the Pin-cells coming up on that process ?