An implementation of MUL / MULS
Willy Ekerslyke
Posts: 29
I've implemented the MUL / MULS instruction. See attached zip for the modified cog.v and cog_alu.v files. I've marked the non-obvious changes with a // MUL comment. There's also a .spin test program that I used but it outputs to the 16x2 LCD on my Cyclone III board so you'll have to change it to suit your output device.
It's a full 32 x 32 bit multiplier so I've used the carry effect (wc) bit to select which 32 bits become the result: wc == 1 -> high 32 bits, wc == 0 -> low 32-bits. The zero flag is set (if enabled) according to the full 64-bit result. The carry flag always remains unaltered.
Uses 8 multiplier elements per COG. I've not done any speed assessments but as it's almost certainly the slowest part of the ALU it will undoubtedly limit the max COG clock.
It's a full 32 x 32 bit multiplier so I've used the carry effect (wc) bit to select which 32 bits become the result: wc == 1 -> high 32 bits, wc == 0 -> low 32-bits. The zero flag is set (if enabled) according to the full 64-bit result. The carry flag always remains unaltered.
Uses 8 multiplier elements per COG. I've not done any speed assessments but as it's almost certainly the slowest part of the ALU it will undoubtedly limit the max COG clock.
Comments
I will add this to my p1v and test.
So far we have: unscrambled rom, portb and mul plus these less-than-8-cogs versions...
We also have >2KB per cog, VGA for a single cog (or other mix).
Think there are a few other things done, including multiple P1s.
Some stuff is overlapping and would probably be non-trivial, but lots of stuff would just work I think.
Some ideas:
- Choose HubMem size
- Choose number of COGs and customize every one of them of needed.
- Choose which ROM-parts to include
assign co = i[5:1] == 5'b00010 ? ci // mul: more selective -- pass through to ensure carry not altered
: i[5:3] == 3'b000 ? bus_c
: i[5:3] == 3'b001 ? rot_c
: i[5:3] == 3'b011 ? log_c
: add_c;
If you test the i[5:3] before the i[5:1] in the case of your code co is always set to bus_c and not to ci or am I missing something?
I'm pretty sure my code is ok:
assign co = i[5:2] == 4'b0000 ? bus_c // MUL: more selective : i[5:1] == 5'b00010 ? ci // MUL: pass through to ensure carry not altered : i[5:3] == 3'b001 ? rot_c : i[5:3] == 3'b011 ? log_c : add_c;bus_c is only selected if the four bits 5:2 are all zero otherwise ci is selected if the five bits 5:1 are 00010 etc.