AHDL help needed

nutson

I am stuck with AHDL. I want to add three pins to the top level module, and use those in the dig.v module but I keep getting compile errors.

The three pins / signals have been added to the top.tdf file as follows

subdesign top
(	clock_50			: input;		-- clock input
	inp_resn			: input;		-- reset pin
	io		[31..0]	: bidir;		-- i/o pins
	ledg	[7..0]	: output;	-- cog leds
	
	dbgdata			: output;
	dbgclock		   : input;
	dbgstart		   : input;
	)

and in the dig.v as follows

module				dig
(
input					nres,			// reset input (active low)
output	 [7:0]	cfg,			// configuration output (set by clkset instruction)
input					clk_cog,		// cog clock input
input		 			clk_pll,		// pll simulator clock input (2x cog clock)
input		[31:0]	pin_in,		// pin state inputs
output	[31:0]	pin_out,		// pin state outputs
output	[31:0]	pin_dir,		// pin direction outputs

input 				dbstart,
input					dbclock,
output				dbdata,

output	 [7:0]	cog_led	);	// led outputs to show which cogs are active

and connected in the top.tdf file with

-- debug pins
	
	dbgdata			= core.dbdata;
	core.dbclock	= dbgclock;	
	core.dbstart	= dbgstart;

Quartus keeps complaining

Error (287071): Symbolic name "dbdata" must be port of megafunction, macrofunction, primitive, or state machine "core"
Error (287071): Symbolic name "dbclock" must be port of megafunction, macrofunction, primitive, or state machine "core"
Error (287071): Symbolic name "dbstart" must be port of megafunction, macrofunction, primitive, or state machine "core"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings

What I am doing wrong??

pik33

.inc files need update too

jac_goudsmit

Also you probably need to update the top.qsf file to specify where the new pins are assigned (I think it's possible to do this from inside Quartus too but I forgot how).

===Jac

Yanomani

nutson

I'm no expert in AHDL, but from my readings about syntax, the problem seems to be at your version of dig.v
It's a little subtle, but it appears to be about the position of the ");" in between "output [7:0] cog_led" and "// led outputs to show which cogs are active".
IMHO it should read:

module                dig
(
input                    nres,            // reset input (active low)
output     [7:0]    cfg,            // configuration output (set by clkset instruction)
input                    clk_cog,        // cog clock input
input                     clk_pll,        // pll simulator clock input (2x cog clock)
input        [31:0]    pin_in,        // pin state inputs
output    [31:0]    pin_out,        // pin state outputs
output    [31:0]    pin_dir,        // pin direction outputs

input                 dbstart,
input                    dbclock,
output                dbdata,

output     [7:0]    cog_led       // led outputs to show which cogs are active
);

I've checked at the original 60050,60056-Propeller-1-Design-2014-08-11 and it's written this way there.

Since I've no means of testing it, I'm letting to you to verify it works.

Fingers crossed here!

Yanomani

nutson wrote: »

I am stuck with AHDL. I want to add three pins to the top level module, and use those in the dig.v module but I keep getting compile errors.

The three pins / signals have been added to the top.tdf file as follows

subdesign top
(    clock_50            : input;        -- clock input
    inp_resn            : input;        -- reset pin
    io        [31..0]    : bidir;        -- i/o pins
    ledg    [7..0]    : output;    -- cog leds
    
    dbgdata            : output;
    dbgclock           : input;
    dbgstart           : input;
    )

and in the dig.v as follows

module                dig
(
input                    nres,            // reset input (active low)
output     [7:0]    cfg,            // configuration output (set by clkset instruction)
input                    clk_cog,        // cog clock input
input                     clk_pll,        // pll simulator clock input (2x cog clock)
input        [31:0]    pin_in,        // pin state inputs
output    [31:0]    pin_out,        // pin state outputs
output    [31:0]    pin_dir,        // pin direction outputs

input                 dbstart,
input                    dbclock,
output                dbdata,

output     [7:0]    cog_led    );    // led outputs to show which cogs are active

and connected in the top.tdf file with

-- debug pins
    
    dbgdata            = core.dbdata;
    core.dbclock    = dbgclock;    
    core.dbstart    = dbgstart;

Quartus keeps complaining

Error (287071): Symbolic name "dbdata" must be port of megafunction, macrofunction, primitive, or state machine "core"
Error (287071): Symbolic name "dbclock" must be port of megafunction, macrofunction, primitive, or state machine "core"
Error (287071): Symbolic name "dbstart" must be port of megafunction, macrofunction, primitive, or state machine "core"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings

What I am doing wrong??

nutson

Thanks all for your time and attention. The winner is: pik33. After editing the dig.inc file, and adding the new nets to the dig.v input / output definition, the project compiles fine. An of course in the pinplanner I needed to setup which pins of the FPGA are to be used. Will inform you later what the project is.

ozpropdev

Use File - Create/Update - Create AHDL Include file for the current file