AUGDS instruction for P1V
Cluso99
Posts: 18,069
I am going to implement this instruction in the P1V. It will be a bit different to the P2.
AUGDS #/D,#S WC,WZ
D & S will both be either immediate 9 bit values or both register addresses. A mix will not be permitted.
This will preset bits [17:9] for D & S in the following instruction only. Of course its usage depends on the insttruction.
WC & WZ are potential later instruction options and do not change Z or C flags.
More info to come later. gtg
AUGDS #/D,#S WC,WZ
D & S will both be either immediate 9 bit values or both register addresses. A mix will not be permitted.
This will preset bits [17:9] for D & S in the following instruction only. Of course its usage depends on the insttruction.
WC & WZ are potential later instruction options and do not change Z or C flags.
More info to come later. gtg
Comments
The AUGDS instruction would set two internal registers...
for immediate mode...
augd[31:0] <= 14'b0, i[17:9], 9'b0 // set to #D
augs[31:0] <= 14'b0, I[8:0], 9'b0 // set to #S
else...
augd[31:0] <= d[31:0] // set to value in register D
augs[31:0] <= s[31:0] // set to value in register S
The following instruction will...
ADD augd[31:0] and d[31:0] to give a new resulting d[31:0] value
ADD augs[31:0] and s[31:0] to give a new resulting s[31:0] value
The instruction will then use these resultant d & s values in the execution of the instruction.
I had a lot of problems finding a way to verify this was working. Many bugs just getting to see that what I had done was indeed functioning, and where I had a problem when it didn't work as I expected.
Looking forward to posting progress shortly
Looking forward to seeing your work.
I'm currently working on a variant that supports full 10 bit addressing of D & S (1024 longs of cogram).
Half way there, so far so good. have to rewrite booter and spin interpreter to suit changes. Yikes!
Interesting challenge but learning as I go....
Cheers
Brian
AUGSD info...
iiiiii zcri cccc dest..... source
000110_0001_1111_ddddddddd_sssssssss
Currently, when executed...
1. The values of "ddddddddd" and "sssssssss" are saved in registers for the next instruction only.
2. If only D or S is required, then the other should be 0.
3. When the next instruction is fetched, the "sssssssss" value is extended by the aug S<<9 to make an 18 bit S value.
4. And "ddddddddd" is extended by the aug D<<9 to make an 18 bit D value.
5. This means that the S value of the instruction following the AUGDS instruction can now have an 18 bit immediate S value.
6. If Cog RAM is >2KB, then the extended S & D addresses will be truncated to the address bits required for the cog. This means all usual instructions such as MOV, ADD, etc can access the additional cog RAM although MOVS/MOVD/MOVI (and perhaps others) may have side effects.
7. This will permit the JMPRET (JMP/CALL/RET) instruction to be preceeded by an AUGDS instruction to extend its range within the cog RAM.
8. AUGDS only works for immediate mode (ie the D and S values are effectively both immediate values and are not used to fetch values in registers)
9. Currently AUGDS does not work conditionally (ie cccc=1111=always and is not tested).
I intend to add a JMPRETX (JMPX/CALLX/RETX) instruction to support hubexec.
For now, I need to expand the pc and cog ram to verify the correct working of AUGDS and other instructions.I have verified its basic functionality
I am going to test a cog with 8KB RAM
If this will work we will have a (near) full backward compatible Propeller cog. To enter extended mode, jmp #inb. To exit extended mode, jmp outside inb.
The first try caused the Propeller non programmable, don't know why. So, in the next try I will modify only Cog 7 and check what is wrong.
Interesting concept. I will keep watch to see how your version goes.