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free verilog synthesis tools (P1V into ASIC, wip) — Parallax Forums

free verilog synthesis tools (P1V into ASIC, wip)

RamonRamon Posts: 484
edited 2014-08-22 15:18 in Propeller 1
Today I didn't have time to work with the xilinx port. I was exploring this:

http://opencircuitdesign.com/qflow/

From Verilog to standard cell IC Layout using free tools (sw and standard cell libraries too).

Still work in progress ...

Comments

  • AntoineDoinelAntoineDoinel Posts: 312
    edited 2014-08-21 14:09
    Ramon wrote: »
    Today I didn't have time to work with the xilinx port. I was exploring this:

    http://opencircuitdesign.com/qflow/

    From Verilog to standard cell IC Layout using free tools (sw and standard cell libraries too).

    Still work in progress ...

    Back in the bronze age I used to mess with this for was an uni exam assignment:

    http://www-soc.lip6.fr/recherche/cian/alliance/

    task was to implement the spatial filtering portion of an audio beamformer, in VHDL, up to timing simulation.
    No real implementation, FPGAs were too small back then anyway.

    I remember it had nice text utilities to generate memories, multipliers, etc.

    I've heard that it has been used to produce some real silicon (a RISC processor IIRC).
  • cgraceycgracey Posts: 14,155
    edited 2014-08-22 12:38
    We looked into getting a complete set of Verilog-to-GDSII tools at Parallax from one of the big vendors. It came to $300k per year - and that was at 50% off!
  • Cluso99Cluso99 Posts: 18,069
    edited 2014-08-22 15:18
    cgracey wrote: »
    We looked into getting a complete set of Verilog-to-GDSII tools at Parallax from one of the big vendors. It came to $300k per year - and that was at 50% off!
    Cheaper to pay someone with a license to do it with you sitting beside them ;)
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