Where to define some parameters in verilog - No of Cogs, Hub size, etc
Cluso99
Posts: 18,069
It would be nice to have some variable parameters defined in a top object somewhere.
Those with verilog experience, where is the best place? top.v or elsewhere???
What instructions will do this? ie use a DEFINE or similar. I am going to look at this today when I get a few moments as I cannot compile code today as I am out.
Those with verilog experience, where is the best place? top.v or elsewhere???
What instructions will do this? ie use a DEFINE or similar. I am going to look at this today when I get a few moments as I cannot compile code today as I am out.
Comments
1) One way (the way I've done locally for now) is, as you say to use define at the top of each file.
2) Or in a seperate file from where you include it like:
#include "defines.inc"
for each file that need any of these defines.
3) Another way is to use the environments special fieds for defines. Then these defines become part of the project files.
This maybe nice if using the same source files for many target-FPGA within the same environment.
Anyone else?
Can you post a bit of sample code?
As I mentioned here, I'm setting up a Github repo that builds the P1V targerts in the way Chip intended, but can be modified easily when you want to change features like number of cogs, amount of hub RAM etc. but I'm new to Verilog and AHDL (I can kinda read it but not write it yet) so some pointers would be helpful.
===Jac