Additional counters per cog - any showstoppers?

pmrobert

I'll be spending some quality time with the codebase tomorrow seeing if adding additional counters to a cog is feasible. Does anyone have any preliminary advice and/or pointers?

-Mike

rogloh

Do you plan to sacrifice some COG memory below $1F0 for your new counter registers? If not, how else will you address them? If so, some existing objects needing all $1F0 registers may break, or start potentially driving new counter outputs. If you only run your own COG PASM code exclusively that may not be an issue.

Phil Pilgrim (PhiPi)

You could map as many register banks to 1F0-1FF (or a subset thereof) as you want by writing a pointer to the shadow register of one of the read-only registers, such as cnt.

-Phil

Tubular

Very good idea, Phil. That would really open things up.

pmrobert

That sounds like a great approach and it sounds like it doesn't break the HLLs.

Lawson

Phil Pilgrim (PhiPi) wrote: »

You could map as many register banks to 1F0-1FF (or a subset thereof) as you want by writing a pointer to the shadow register of one of the read-only registers, such as cnt.

-Phil

Uh, doesn't the Spin interpreter use the CNT shadow register as a loop counter? Sounds like this would break counter support in spin at least. (though the INA or INB shadow register may be free)

Marty

abecedarian

Lawson wrote: »

Uh, doesn't the Spin interpreter use the CNT shadow register as a loop counter? Sounds like this would break counter support in spin at least. (though the INA or INB shadow register may be free)

Marty

I don't believe Spin is being used here so this shouldn't be a issue.
pmrobert can clarify.