ROM files (unscrambled) and verilog changes for increased Hub RAM

Cluso99

Over on this thread I asked Chip for information to prepare the ROM hex files unscrambled. He graciously provided all the details to rebuild these files.
http://forums.parallax.com/showthread.php/156866-Question-for-Chip-re-ROM-code
I thought this information deserved it's own thread, together with a better title.

I have modified the two verilog files "hub.v" and "hub_mem.v" to
1) Remove the unscrambling code
2) Modify the Hub Memory to only use RAM, and that the top 4KB of RAM is remapped to $F000..$FFFF also.
3) Provided four files "ROM_$F000-$FFFF_BYTE0.spin" to "ROM_$F000-$FFFF_BYTE3.spin" that are the Hex ROM files

RR20140816g_ROM_$F000-$FFFF_BYTE_x.zip

This enables you to build a P1 with 48KB of hub RAM $0000..$9FFF.
It is simple to change the size of the hub RAM for other builds.
ROM $F000..$FFFF is mapped to the top 4KB of hub RAM (eg 44-48KB $9000..$9FFF).
This means that the Interpreter, Booter and Runner code is available at the same P1 ROM addresses within $F000..$FFFF.

Enjoy

mindrobots

Thanks Ray!

I'm going to try integrating this and my PortB changes and whatever else is floating around into one big mess! This will obviously lead me down a perilous path with no certain outcome but it will be a fun adventure!

Bill Henning

Thanks Ray - nice work!

Cluso99

Just needed to pass this on to Jac, so thought I would post here too...
This is the code I use in hub_ram.v with a parameter HUBSIZE declared in dig.v

parameter HUBSIZE = 48; // hub ram size in KB

// 12,288 x 32 (48KB) ram with byte-write enables ($0000..$BFFF)
reg [7:0] ram3 [(HUBSIZE/4)*1024-1:0];    // 4 x 12KB
reg [7:0] ram2 [(HUBSIZE/4)*1024-1:0];
reg [7:0] ram1 [(HUBSIZE/4)*1024-1:0];
reg [7:0] ram0 [(HUBSIZE/4)*1024-1:0];

// pre-load ROM (44-48KB RAM dual mapped to 60-64KB ROM)
initial
begin
    $readmemh ("ROM_$F000-$FFFF_BYTE_0.spin", ram0, ((HUBSIZE/4)-1)*1024);
    $readmemh ("ROM_$F000-$FFFF_BYTE_1.spin", ram1, ((HUBSIZE/4)-1)*1024);
    $readmemh ("ROM_$F000-$FFFF_BYTE_2.spin", ram2, ((HUBSIZE/4)-1)*1024);
    $readmemh ("ROM_$F000-$FFFF_BYTE_3.spin", ram3, ((HUBSIZE/4)-1)*1024);
end

// remap RAM/ROM: 48-64KB overlays 32-48KB
wire [13:0] addr = !a[13] ? a[13:0] : {2'b10, a[11:0]};    // do this manually for hubsize!!!    

jac_goudsmit

Thanks Ray!

I already started merging that code into my Cluso99 branch and I already added a parameter too, except I named it something else (parameter CLUSO99_HUBRAM_SIZE_LONGS = 8192 or something :-). I'll finish it this weekend.

I also have my own idea of implementing a backwards-compatible HUB shadow RAM which I'll present here later (I worked until 2AM last night to write the Verilog for it but it doesn't quite work yet). It will make it possible to have up to 64KB of hub RAM without changing the ROM memory map. Stay tuned!

===Jac

Roadster

This is great but I guess open spin will need to change to support large spin program compiles