Can a Crowdsourced chip be developed from the P1 Verilog Code?
Dave Hein
Posts: 6,347
Since Parallax has released the P1 Verilog code, could it be used to produce a chip that outperforms the current Propeller chip? I believe FPGA vendors provide a service that converts an FPGA image to an ASIC, which is smaller, runs faster and is less expensive. Is this a viable approach? It might be possible to fund the development through Kickstarter. Stranger projects on Kickstarter have raised hundreds of thousands of dollars.
The new and improved P1 chip could include a few enhancements, such as a multiplier and port B support. However, the scope of the enhancements would need to be very limited to ensure that the chip becomes a reality.
The new and improved P1 chip could include a few enhancements, such as a multiplier and port B support. However, the scope of the enhancements would need to be very limited to ensure that the chip becomes a reality.
Comments
Then you turn to the Forum fanatical for your crowd sourcing - are we going to pay $10? $12? $14? for a DIP? What if it is not a DIP, then some folks will not be interested since it isn't hobbyist friendly. If it is a SMT package then you are looking at a different (smaller) group of people but they would want more individual chips. The people that can make boards and use in their business or resell to the hobbyists.
You might find some surprise large volume backers {cough,,chip.ken} who might want a considerable inventory of P1.5 chips without bearing the total costs of taking a design to the foundry.
Once a design for a P1.5 can be settled upon....wait, that COULD be the show stopper, then it would be interesting to run the numbers and see.
Plus you need P1.5 T-shirts and snappy videos promoting the chip!
I don't need the chip but a Propeller tee shirt would be great. And a Beanie!
Dang! I forgot the Beanie. That will be for a special reward level!
Kickstarter has the great advantage that you can float a project idea and see what interest there is almost for free. If there is enough interest you get the required cash. If there is not enough interest you get nothing and the backers you did attract don't lose anything. If you do get the money and unluckily it fails with a bad chip or something then the backers have lost their little bet, but I hope they are savvy enough to know that not everything goes the way you expect.
As opposed to having to raise all the money first, sinking it into a chip run and then finding out nobody wants it anyway.
Seems to me it is not something to even think about until a P1++ design emerges that seems to be useful and popular and works. If that ever happens.
I'd certainly be up for punting 100 dollars on a few chips if they were a bit interesting just for the fun of it.
Of course it need not be Parallax that organizes such a kickstarter but I'd feel better if they were behind it.
@Heater: thanks for offering a positive vibe for the doubters you've encountered out there on the 'net. I read it all.
Ken Gracey
Agree, and I think that Parallax missed a good oportunity to raise a crowdfunding campaign. They would have much more media attention if they had released the Verilog code of Propeller and at the same time start a crowdfunding campaign.
There's a nice webpage on FPGA to ASIC conversion at On Semiconductor. It claims that one of the advantages of an ASIC is a 3x to 4x power reduction. It also states that cost reduction would be 25% to 75% of the cost of the FPGA. A 25% cost would be significant, but a 75% cost would hardly be worth it. It's interesting that they don't say anything about higher speed. I assumed that an ASIC would run faster than an FPGA, but that may not be the case. Check out the FPGA-to-ASIC Conversion Reference Manual for more detail on how the process works.
Someone would have to manage all the technical details, but how much?
Thing is campaigns are really marketing things. Parallax stands to benefit from the sales generated from exposure. Anything that increases sales is good (with reasonable investment of course).
What really needs to happen is those of us who really want to see something need to realize it in Verilog. Once that's done, and the FPGA is compelling, that is the time to raise the funds, because then we know what we are selling to people.
No need to thank me. I just say things as I see them. Plus I have this obsessive compulsive desire to correct all wrong statements and misunderstandings on the net. It's a sickness.
@Ramon,
I cannot agree. Throwing a kickstarter in at the time of the open source P1 announcement would have been a very bad idea.
What would one be offering?
Well, we have this P1 design that can be made into a chip. No point in that we already have a P1 chip.
OK, perhaps, we have this P1 design and if you give us a million dollars we can develop it into a P1++ or whatever. That's no good because nobody knows what a P1++ might me or how long it might take to develop. Altogether a huge commitment an too high a risk.
And besides, that all distracts from the current P2 project.
As potatohead says it's far better to wait and see what happens in open source development. See what people want. See what can actually be made. If something attractive, solid, practical and popular emerges then is the time to think about presenting it as a kickstarter. Then you have an interesting idea that people might bite on.
That is when Ken/Chip can look at everything and see what additions they like and may add to an actual P1.5 they do.
AND/OR
A group is organized to take the best of the best to make a solid 'running in FPGA' design and then fire up a KickStarter to see if it can be funded to make chips. If doing that I would suggest targeting a nice big BGA package and do a carrier board as part of the project. Something flexible in layout that would be equally suited for hobby and commercial designs.
The hard part will be selecting which cool ideas to include...
and the "few enhancements" is a second chestnut..
Add onto those, that Logic ASIC flows have no analog, and you have some large '?' on the whole idea.
Best to let it settle for 6 months, to see what can be done in FPGA, and also see what new FPGA prices are doing.
(the Altera MAX 10 for example ).
A simple clone of P1 is very unlikely to be cheaper in modest volume ASIC, and a more complex clone needs definition first.
When a P1.5 Verilog that is more optimised, and tool and ASIC-friendly emerges, Parallax can easily as OnSemi for a price indication. This would all be unlikely before P2 goes into the FAB.
Altera called it Hardcopy. They no longer offer this. (Go Altera Web>Devices>ASICs)
Xilinx call it EasyPath. This is *not* a real FPGA to ASIC conversion. The chip will be same size, same speed, and same power consumption as the FPGA. And it looks to me that Parallax has no intention to help porting to Xilinx. It has high NRE cost and minimum volume (several tens of K units) before getting any price advantage.
#2 Verilog code is not enough to make a P1 ASIC
Some of you understimate the work that needs to be done to have a complete Propeller. Current verilog is just only for the digital part. The analog part is missing. An independent design will risk 1 or 2 shuttle runs until having a working IC. Parallax will just only need one shuttle run to make a working P1 shrink in 180nm.
#3 On Semi FPGA to ASIC (or any other).
Option a) Considering that we layout our IC (are we able to do that ???).
We: Hi, I have this GDSII file. Please, can you make 5 wafers for me?
ON Semi: eh? Who are you?, What is your company?, How many wafers will you order per year?
We: uhhhh, er, I just have some verilog code and I wonder if I can burn the mask into some glass to play with it and give to my friends too ...
On Semi: (big smile ...)
Option b) We ask them to make the layout.
Wait a momment ... why are we considering to hire a design company to make something that Parallax already can do by themselves? Anyway, is On Semi willing to make for us the design of one of their current customers (Parallax)?
#4 Parallax crowfunding campaign will detract from the P2 effort.
My opinion is that any work done to improve P1, works to improve P2 too.
And maybe this can generate revenue to Parallax too.
#5 Wait some months to see what happens in open source development.
I must agree. We have waited for several years, we can do that. And we have now a very nice toy to play while await.
Also, a crowdfunding campaign needs to be planned several months before. And it looks that they haven't made any plan for a crowdfunding campaign. The free advertisement and viral media attention that the Verilog GPL announcement had is now lost. They can start a crowdfunding campaign tomorrow, but they won't have the same free advertisement as the announcement of the release of the P1 Verilog code had.
Parallax released the P1 code so that the community could take the design in whatever direction they please. It's up to the community to port it to any FPGA or manufacturer they desire. There's has been and will continue to be plenty of help and advice between community members and Chip himself has pointed us in the right direction where necessary.
What's the issue with the Xilinx port anyway?
Potatohead & Heater have answered that already.
I'm not going to say you are wrong and that getting a chip run made is easy. The whole idea is out of my league. But Andreas Olofsson who has designed significant silicon in his time and brought the Parallella to us, via kickstarter as it happens, will tell you that it is within the bounds of possibility to get a chip run made for a few hundred thousand dollars. And that it does not require a huge team to do it. That is how we get the Epiphany chip in the Parallella with it's multicore floating point processor.
Such a chip might not have a very low unit price but I can imagine there is enough interested people in Propeller world who would be prepared to pay up for it just for kicks.
Do watch this fascinating presentation by Andreas where he explains what can be done today.
https://www.youtube.com/watch?v=DX9OMgmedbQ
I have no idea about problems with the analog parts of the Propeller. Who says we need them for this project anyway?
It seems like a direct conversion from and FPGA to ASIC is not a viable idea. However, the Verilog used to generate the FPGA could be applied toward an ASIC.
Can you identify what the analog parts are? I'm assuming the VCOs used with the PLLs are the analog portions. Maybe the pin circuitry that is used for Sigma-Delta A/D conversion requires analog design, but I think this can be done entirely with digital ciruitry. Is there any other portion of the Prop that requires analog circuitry? Are you considering the output pin drivers as an analog component, or is this something that can be described in Verilog?
From your comments about working with OnSemi it seems that Parallax will need to be involved in that portion of the work. It seems like a good approach.
I think the work on P1.5 should be limited in scope, and remain independent from P2. The goal of P1.5 is to provide an enhanced P1, and not incorporate major features of P2.
I'm hoping that we'll see some significant P1 enhancements in FPGA within the next few months, and that 6 months from now we could have an FPGA that most people like and use. The biggest problem is determining what features go into the P1.5, and what features don't make the cut. I think a small group of people along with Parallax would make that decision. This would be similar to the way PropGCC was developed by a small closed group of people along with involvement by Parallax. At that point a Kickstarter campaign could be started, or if there is enough financial support from private investors the project could be funded privately.
Ah, yes. With walnuts, of course. Then again, when you have so much of a particular food, don't you get sick of it? What am I talking about? It's not like I get sick of pizza.
The crowd-sourcing idea would be good for engaging a lot of people and giving them a sense of ownership over the project. The chip would likely incorporate the work of others and the Verilog would be open-source. It would be the first democratization of silicon - or, more like a republic if Parallax is in the middle of it. I suppose it would wind up pulling lots of new users into the fold, as a lot of people would just favor the principle of it all.
Going to DEFCON last weekend was a neat experience. They have shunned corporate sponsorships and kept the atmosphere really energized with motivated people who do things simply for the love of doing them. I think that's where The People are headed. That kind of atmosphere really spoils you and antiquates the old trade-show model, if exchange of ideas is what you're after.
As I said somewhere already Kickstarter might be a great way of flying a chip design and getting a fab run funded. It means that if there is interest you get backers, reach the target and proceed. If you there is not enough interest you don't make the target, everyone keeps their money and it has cost the organizers little. It's very predictable and low risk that way. You don't have to spend the money first and them risk finding it's all a waste because nobody want to buy the thing.
I do like the idea of "engaging a lot of people and giving them a sense of ownership over the project" and "the first democratization of silicon". However I think that the dev work, with all that community input, should be completed and a design finalized before initiating a a KickStarter campaign.
I could imagine that having thousands of backers squabbling over how the design they have put money into should go would be a nightmare. Better to have the design solidified and in the can first.
DEFCON sounds fantastic. Wish I could get there. I just happened to be listening the Chris Gammell on the AmpHour podcast describing his visit to DEFCON this year. Seems he really did not get into the idea or take away from it what you did. "All those people hacking away on things, what are they up to? what's the point?" to paraphrase Chris.
P.S. "The Republic of Parallax" I love it.
I consider analog: VCO, PLLs, ADC and nearby pins (pads). Not sure if there is any other component missing from this list.
The P2 had a lot more (ADC/DAC, XFER, smart pins). For me it is more valuable what can be done in the periphery of propeller die that their core.
If the P1.5 uses the same 350nm process as P1 it could probably use the same pin drivers, PLLs and VCOs that the P1 uses. So now it comes down to the extra features that the P1.5 would have, such as Port B, multiplier, more hub RAM, etc.
===Jac
Part of what stalled P1B was lack of chip wide verification, as you need to merge Hand drawn Cells, with compiled blocks.
Also note the P1 is hand designed, so the present silicon usage will be smaller than a compiled block.
That rather excludes using the same process, as the die is already large.
So one approach is to develop the P1.5 first with the 180nm process. It would contain the P1 core with the P2 peripheral circuitry, plus a few extra features such as a multiplier, port B and more hub RAM. It seems like 60K of hub RAM plus 4K of ROM would be easy to do, and would not require changing the Spin interpreter. I think this approach would get us a P1.5 very quickly, and would provide a way to test out the P2 peripheral circuitry.
With the 180nm process, P1.5 should be able to run faster than P1 -- maybe it could achieve the 200 MHz speed targeted for P2. I think a P1.5 with a hardware multiplier, 200 MHz operating frequency, 64 bits of I/O and 60 KB of hub RAM would be an extremely useful device.