Working with top Verilog modules

nutson

I own several Terasic FPGA boards that all come with demo projects that have a top level Verilog module that conveniently defines names and pins for all the FPGA board resources. .


So I took the DE2-115 Default project from the DE2-115 CD and added the following lines:

top top(CLOCK_50,
GPIO[27],
{GPIO[29],GPIO[31],GPIO[30], GPIO[28:0]},
LEDG[7:0]);

After copying the propeller design files to the DE2-115 folder, and adding the top.tdf file to the project this compiled ok and is running now
(to be honest: there was another assignment to the LEDG pins that had to be removed first)

I now plan to port the propeller design to some other boards, let you know.

pik33

Added top on top of top

nutson

The same method works now on the Cyclone V GX starter kit. The default top level file that Terasic delivers is a mess, they used Qsys to bring in a controller for the HDMI output, and this invokes a complete (time limited) NIOS processor that initialises the HDMI chip. Quartus nearly choked on this. After commenting out the HDMI stuff everything worked fine.

@pik33 Your method of making a symbol of the propeller is ok, only I am working also at the top level with Verilog. And I want to use the onboard resources (SRAM, SDRAM etc) so I wanted to have all the relevant pin names and definitions without duplicating them.

pik33

Open a QSYS, change Nios to version e and it will run. Maybe a HDMI controller can be initialized with a Propeller. No more NIOS, QSYS and Eclipse!

I am now going to make some revolution with the Propeller. After splitting Port B to in and out and testing this (good!) I want to get rid of top.tdf and the pll. Then split port A too, getting separate ina, outa, dira, inb, outb, dirb.

Bidir ports are rare needed in an FPGA environment. Where needed, I can make them outside a Propeller block, making things simpler.

nutson

Good idea, pik33, when we are going to utilize the onboard SRAM and SDRAM we will need a lot of pins == adresses. I was thinking of skipping the first ROM block (character definitions) in all versions and use that address space for on-chip / on-board peripherals that can be adressed by RDLONG / WRLONG instructions

pik33

Maybe it will be a good idea to restrict bidir capabilities to port a only. This will maintain compatibility with existing code. Where needed, we can combine dira[x], ina[x] and outa[x] into bidir io[x] outside the propeller block.
Then we will have two 32 outputs, outb and dirb and one 32 input inb. Address, data in and data out.

Edit: done. Need testing now.
Edit 2: Now I can try to use my old modules intended to use with nios/qsys with the Propeller
Edit 3: DE2-115 SRAM/SDRAM may be available for LMM programs by loading the cog via inb port