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Sync versus async reset of cut in dig.v? — Parallax Forums

Sync versus async reset of cut in dig.v?

KeithEKeithE Posts: 957
edited 2014-08-13 13:19 in Propeller 1
Chip - did you intend for cnt to be reset synchronously in dig.v? It looks like your other resets are all async.
// cnt

reg [31:0] cnt;

always @(posedge clk_cog) // KeithE - sensitivity list only contains the clock
if (nres)
    cnt <= cnt + 1'b1;


// bus enable

reg ena_bus;

always @(posedge clk_cog or negedge nres)
if (!nres)
    ena_bus <= 1'b0;
else
    ena_bus <= !ena_bus;

Comments

  • pik33pik33 Posts: 2,366
    edited 2014-08-13 08:16
    cnt is not resetted here. It only doesn't count when the reset is low.
  • KeithEKeithE Posts: 957
    edited 2014-08-13 08:47
    Too early in the morning… ;-)

    (It would make gate sims fun.)
  • pik33pik33 Posts: 2,366
    edited 2014-08-13 08:51
    Good morning.. or maybe evening, 5.50PM here and some headache after fighting with the P1V, SD card, WM8731 soundchip and PS2 keyboard which I tried to connect to it.
  • RamonRamon Posts: 484
    edited 2014-08-13 08:57
    Where is cnt resetted to zero?
  • pik33pik33 Posts: 2,366
    edited 2014-08-13 09:06
    Maybe nowhere. I can't find it now.
  • mindrobotsmindrobots Posts: 6,506
    edited 2014-08-13 09:29
    Does it need to be? It just runs....or doesn't run in the case of a reset condition. Its value is really just relative to the last time you looked at it (unless that was more than 53 seconds ago).

    I haven't seen anyplace where it gets set to 0.
  • KeithEKeithE Posts: 957
    edited 2014-08-13 10:16
    I think that Chip doesn't care about the power-up or reset value. It is a problem if you're trying to run simulations though - in this case it would be for both behavioral and gate-level simulations. Since Chip doesn't run simulations he hasn't seen this issue.
  • cgraceycgracey Posts: 14,155
    edited 2014-08-13 10:22
    The CNT never gets reset, since it's only used for relative measurements.

    This Verilog code represents what is actually in the P8X32A chip.
  • mindrobotsmindrobots Posts: 6,506
    edited 2014-08-13 10:30
    KeithE wrote: »
    I think that Chip doesn't care about the power-up or reset value. It is a problem if you're trying to run simulations though - in this case it would be for both behavioral and gate-level simulations. Since Chip doesn't run simulations he hasn't seen this issue.

    If you need a CNT that starts at 0 on reset, then you can add that for your simulations. It sure won't hurt anything in your simulated propeller. That's the wonderful thing about having a P1 in Verilog!! :lol:
  • KeithEKeithE Posts: 957
    edited 2014-08-13 10:31
    Note that one could use $deposit from a testbench to initialize cnt at power-up in simulations, or edit the verilog.

    The problem is that cnt will stay at X in simulations otherwise.
  • pik33pik33 Posts: 2,366
    edited 2014-08-13 10:57
    Add
    initial
  cnt<=0;

    and it will start with 0

    Add if (!nres) cnt<=0 and it will be zero at every reset.
  • Cluso99Cluso99 Posts: 18,069
    edited 2014-08-13 13:19
    IIRC cnt on the P1 starts with a random value.
    That is what Chips reply means. Its normally not relevant.
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