simulate P1 with SystemC
Reinhard
Posts: 489
For years I was looking for a larger project to go into SystemC.
Now I have found one;-)
Verilator is an open source software and translated
Verilog by SystemC.
verilator --sc * .v
Thus, one can from the Verilog modules make an executable file.
SystemC files can be re-compiled and synthesized with Verilog or VHDL.
Possibly can anyone enthusiastic about this idea.
Primarily it is intended for learning purposes.
Thank Parallax
Now I have found one;-)
Verilator is an open source software and translated
Verilog by SystemC.
verilator --sc * .v
Thus, one can from the Verilog modules make an executable file.
SystemC files can be re-compiled and synthesized with Verilog or VHDL.
Possibly can anyone enthusiastic about this idea.
Primarily it is intended for learning purposes.
Thank Parallax
Comments
Compile that into JavaScript with Emscripten and we can run the P1 in the web browser!
As we already have a Spin IDE running in the browser being able to add a simulator would be great.
But until then, there is still a long, hard road.
Right now all I can v-files individually translate
and get the h and cpp files.
During compilation of the top files <top.tdf ??> I get error messages.
Tonight I'm going to have verilator man-pages read accurately;-)
Ok, that looks a great idea.
There probably is a clever way of getting everything to work in parallel. eg in vhdl or Verilog, lots of processes are synchronised to a clock transition. So the clock changes, and other things change, but then they stop changing until a clock changes again. I don't know how systemC solves that. Maybe you go through all the things that change on a clock change and do them one at a time. They tend to be encapsulated in processes. I'm probably not making much sense - in my defence I just spent a whole day coding in vhdl. But I can see how it could be done in something like systemC, and it would be fantastic to get a propeller emulation working in this way.
I don't know about getting it to run at 80Mhz on javascript though...
As far as I can tell Verilator translates Verilog into C++ or SystemC (Which is C++ anyway) which you can then compile and run as a normal executable on your PC. I would be surprised if it can get anywhere near the real speed of a Propeller even if you do have an 8 core 4GH Intel box.
You would be surprised at the speed of C/C++ compiled to JavaScript and run under the JS engines in Firefox or Chrome. Some examples approach half the speed of natively compiled code on the same machine. The OpenSpin compiler, C++, is plenty fast enough to be usable when compiled to JS.
If Verilator translated code can make use of multiple cores though JS will have a hard time keeping up as there is no easy way to use more than a single core.
Still, for a simulator to help with debugging it might still be if use even if it is slow. Sounds like it's going to happen anyway
re:I don't know about getting it to run at 80Mhz on javascript though
Maybe:
asm.js is an intermediate programming language consisting of a strict subset of the JavaScript language. It enables significant performance improvements for web applications which are written in statically-typed languages with manual memory management (such as C) and then translated to JavaScript by a source-to-source compiler. Asm.js does not aim to improve the performance of hand-written JavaScript code, nor does it enable anything other than enhanced performance.
http://en.wikipedia.org/wiki/Asm.js
With a bit of C / C ++ experience the training period is a few days.
2; The bottleneck;-(
download verilator
Either the classic way:
./configure
make
make install
or verilator is in your distribution.
Unfortunately my verilog translation -> SystemC is not yet
successful.
C++ is a big and complicated language, derived from C, that no human being will ever live long enough to fully comprehend. It enables object oriented programming if you like. It enables template meta programming if you like. It generally compiles down to native machine code that can give you slim and fast executables and give you as much control of your hardware as a high level language can.
Java is a big and complicated language, sort of derived from C++, that no human being will ever live long enough to fully understand. It totally insists on the brain dead paradigm of object oriented programming for everything. It generally compiles down to byte codes which then have to be interpreted by some huge and slow virtual machine. It keeps you as far away as possible from control of your machine as a high level language can.
Not only that. On top of all the inconvenience of Java it has no reason to exist at all. It brings no interesting or useful features to the programming language world.
Not only that but Java was supposed to be "Write once run anywhere", however it does not run on most machines of interest unlike C++. Java is totally pointless.
Oh, sorry I forgot to put this at the top "WARNING Language War imminent."
By the way, who mentioned Java here? There was mention of JavaScript which is a much more interesting and sophisticated language than Java can ever imagine. Which also happens to be more cross platform than Java as a bonus.
Yes I did mean Java Script. Didn't realize there was a difference. Guess I should stick to art and coax but my afpga board just arrived so the learning may start!!
PS got the files downloaded and extracted. Heaven help me...
Qt(C++) --->
Here's the official reason.
Brendan Eich created JavaScript in 1995 with the aim to provide a "glue language" for Web designers and part time programmers
Why was JS originally named Mocha and then LiveScript?
Mocha was Marc Andreessen's code name, but Netscape marketing saw potential trademark conflicts and did not prefer it on other grounds. They had a "live" meme going in their naming (LiveWire, LiveScript, etc.). But the Java momentum of the time (1995-1996) swept these before it.
http://www.computerworld.com.au/article/255293/a-z_programming_languages_javascript/
I will be quiet for awhile.........
W 8.1 is not that much better
Sorry, just had to get the frustration off my chest.
Back to the topic on hand.....
Sounds really interesting, but I will have to let you all do this.
This thread is about SystemC. It is a hardware tool used mostly in simulation/verification and has little to do with C (much less C++) programming in the usual sense other than similar syntax. Java and Javascript have nothing to do with SystemC.
:frown:
Forgive me if I'm wrong but "SystemC is a set of classes and macros which provide an event-driven simulation interface in C++". According to wikipedia at least.
Meanwhile: "Verilator compiles synthesizable Verilog into C++ or SystemC code." According to the Verilator web site.
And as we know C++ can be compiled to JavaScript with LLVM and Emscripten. See OpenSpin.js
Which gives rise to the chain of thought:
Verilog -> C++/SystemC -> JavaScript
That is to say. The Open Source P1 design running in the browser.
This may be an insane idea, but if someone is mad enough to get the P1 Verilog through Verlator into C++/SystemC then I'm mad enough to get that through Emscripten into the browser.
It will happen.
But yes you are right. Java has nothing to do with this:)
Ooops. Didn't realize you innocently started this mess.
Yes, SystemC is used for simulation and testing. It has been for about 14 years in various places. It was slowly adopted because of industry momentum in verilog/vhdl.
Back to the regular thread.
In another thread I read the files top.tdf and tim.tdf are written in AHDL.
This could be the reason why the verilator gets out.
I really need a verilog expert, I am not, unfortunately.
If we have the P1 description in SystemC / C ++,
then could bring the prop-emulator to run an army of programmers.
While trying to port the whole project to Xilinx ISE development environment I'm also got aware of SystemVerilog parts (SystemVerilog is not suppported in Xilinx ISE) of the code and that the ROM are intialized in a Quartus specific way.
The things I've already done locally are:
- Running Xilinx xport.exe command-line tool and tried to auto-convert AHDL => Verilog. Some parts seem to work, some didn't.
- Convert different syntaxes from SystemVerilog to Verilog. multi-dim syntax, variables declared before use and others..
- Converted in init parts to "regular" verilog $readmemh() which actually works for both environments. This also included the work of converting the hex-files from Intel-Hex format to simpler one-line format. Done!
- Xilinx specific re-writes of PLL.
No code share yet on these but I'll make them public when I have some kind of progress with actually running them in the Xilinx FPGA. I shall try and do that this weekend.
It seems like one of the key things for several of the small projects here in the forum is to have a perfectly working verilog-only version of the P1.
I don't want to be the one to judge AHDL-files, so as I see it, we make a branch from a suitable Github project in which we move away from both AHDL, specific Altera commands and SystemVerilog.
Anyone know of a github repository that mirrors the release files from Parallax? This would be a good start. Preferebly with the, for now, latest bug fixes.
I have put the P1 design up on github here: https://github.com/ZiCog/P8X32A_Emulation
It is basically the original code with the tab/space problems fixed.
It is possible that Chip will take ownership of that repository soon. After he has a while to rest and think about it. Or he might not....
You could always fork from my repo and do whatever you like in your copy. Perhaps it happens that Parallax takes over my repo and then if your changes are nice they can be pulled from your repo directly in to Parallax's.
1) Download the code from this thread:
http://forums.parallax.com/showthread.php/157004-Propeller-1-running-on-Pipistrello-(Xilinx-Spartan6-LX45)
2) Add "/* verilator lint_off WIDTH */" to cog_vid.v, cog_ctr.v, cog.v and hub.v
(Small changes to the code to avoid this compiler warning)
3) Substitute line 108 of cog_vid.v with this lines:
/* verilator lint_off UNOPTFLAT */
reg [1:0] snc;
/* verilator lint_on UNOPTFLAT */
4) Substitute line 52 of cog_vid.v whit this lines:
/* verilator lint_off UNOPTFLAT */
reg [31:0] vid;
/* verilator lint_on UNOPTFLAT */
5) Now run verilator on dig.v
$ verilator -cc dig.v
Enjoy!
It works, but do not know how to use it, as I don't know anything about C++, SystemC or SystemPerl. But I am sure there will be someone here that knows how to use it