Features like smart pins could be played with using FPGA. Unfortunately, to do so probably means open sourcing SPIN and pasm.
Smart pins are still a new P2 feature. To play with them in FPGA we would need the verilog source and I hope Parallax is still keeping that under wraps.
Smart pins are still a new P2 feature. To play with them in FPGA we would need the verilog source and I hope Parallax is still keeping that under wraps.
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Smart pins are still a new P2 feature. To play with them in FPGA we would need the verilog source and I hope Parallax is still keeping that under wraps.
Ot make them ourselves if needed