Experiments in porting Prop1 to an XC3S100E FPGA
doggiedoc
Posts: 2,241
This is a work in progress with intent of documenting my learning process spurred by the release of the Parallax Propeller 1 Design.
Goal(s):
Learn more about FPGA, Propeller 1 Design, and Verilog while limiting my cost (initially) by experimenting with the hardware I already own.
Hardware:
FPGA Board - BASYS with Xilinx Spartan XC3S100E from Digilent, Inc
System:
Windows 7 VM on MacBook Pro, MacOS 10.9.4
Software:
Diligent Adept v2.3
Current Status:
efforts abandoned - see this thread
_______
Paul
Goal(s):
Learn more about FPGA, Propeller 1 Design, and Verilog while limiting my cost (initially) by experimenting with the hardware I already own.
Hardware:
FPGA Board - BASYS with Xilinx Spartan XC3S100E from Digilent, Inc
System:
Windows 7 VM on MacBook Pro, MacOS 10.9.4
Software:
Diligent Adept v2.3
Current Status:
efforts abandoned - see this thread
_______
Paul
Comments
My next step, I believe is to get Quartus installed/working. If I understand the process correctly I need to compile the source files with Quartus. I have downloaded these source files from Parallax.
You have to rewrite top AHDL files to Verilog or something Xilinx can understand - Xilinx don't understand Altera's AHDL. (as far as I know, I haven't any xilinx fpgas and tools now)
Thanks again.
http://forums.parallax.com/showthread.php/156842-Xilinx-port-started...