Just fired up a DE0 P1 on Linux Mint for the first time - now where?
Peter Jakacki
Posts: 10,193
Hi Guys, I was hanging around in the wee hours of last Thursday morning waiting for the big news but I had to sleep. As much as I have been wanting to get into the FPGA P1 I've been having all kinds of operations on my one good eye as the other one looks good but the retina was bunged up by a football years ago and although I can see with it I can't use it to read. So it's an ongoing saga at the moment but the good news is that I finally got around to running Quartus on Linux Mint and getting all the setup and permissions right to try out programming a DE0 first.
Got it working!
Previously I took the easy way with the old P2 and installed all this in a WIN7 machine.
So I loaded on Tachyon Forth and that looks good, I can see the gap in the ROM and of course notice that the EEPROM is not emulated but an .I2CBUS scan acks on all addresses although the ports report the I2C lines floating high. Something to look into.
So I'm going to be playing around and testing this on the DE2-115 as well but I might even get the BE Micro CV if they are still available. After I check it out a bit more then I'm thinking of playing with the Verilog files to see what I can do if I had an instruction set optimized for my Tachyon VM, remember that Forth is actually the higher levels of that VM. I also don't see why the VM opcodes couldn't be used by a C compiler either, it's just another "CPU". So if I find some time I might look at writing a simple C compiler to do just that.
I'd like to catchup on a lot of these posts but I might not be able to in the short term but I would appreciate any tips in the meantime.
Got it working!
Previously I took the easy way with the old P2 and installed all this in a WIN7 machine.
So I loaded on Tachyon Forth and that looks good, I can see the gap in the ROM and of course notice that the EEPROM is not emulated but an .I2CBUS scan acks on all addresses although the ports report the I2C lines floating high. Something to look into.
[FONT=courier new]I/O Port states [/FONT] [FONT=courier new]+----------u----------+ P00 <-- 1X 1 --> P31 P01 <-- 1X 1 <-- P30 P02 <-- 1X X1 --> P29 P03 <-- 1X X1 --> P28 P04 <-- 1X X1 --> P27 P05 <-- 1X X1 --> P26 P06 <-- 1D X1 --> P25 P07 <-- 1X X1 --> P24 P08 <-- 1X X1 --> P23 P09 <-- 1X X1 --> P22 P10 <-- 1X X1 --> P21 P11 <-- 1X X1 --> P20 P12 <-- 1X X1 --> P19 P13 <-- 1X X1 --> P18 P14 <-- 1X X1 --> P17 P15 <-- 1D X1 --> P16 +---------------------+ Special function registers 01F0: PAR = $0000_16E8 00_0000_0000_0000_0001_0110_1110_1000 01F1: CNT = $15B7_8F8A 01_0101_1011_0111_1000_1111_1000_1010 01F2: INA = $FFFF_FFFF 11_1111_1111_1111_1111_1111_1111_1111 01F3: INB = $0000_0000 00_0000_0000_0000_0000_0000_0000_0000 01F4: OUTA = $7000_0000 11_0000_0000_0000_0000_0000_0000_0000 01F5: OUTB = $0000_012D 00_0000_0000_0000_0000_0001_0010_1101 01F6: DIRA = $4000_0000 00_0000_0000_0000_0000_0000_0000_0000 01F7: DIRB = $0000_0000 00_0000_0000_0000_0000_0000_0000_0000 01F8: CTRA = $0580_0000 00_0101_1000_0000_0000_0000_0000_0000 01F9: CTRB = $0000_0000 00_0000_0000_0000_0000_0000_0000_0000 01FA: FRQA = $4000_0000 00_0000_0000_0000_0000_0000_0000_0000 01FB: FRQB = $0000_0000 00_0000_0000_0000_0000_0000_0000_0000 01FC: PHSA = $8000_0000 00_0000_0000_0000_0000_0000_0000_0000 01FD: PHSB = $0000_0000 00_0000_0000_0000_0000_0000_0000_0000 01FE: VCFG = $2000_0000 10_0000_0000_0000_0000_0000_0000_0000 01FF: VSCL = $0000_1F40 00_0000_0000_0000_0001_1111_0100_0000 ok[/FONT]
So I'm going to be playing around and testing this on the DE2-115 as well but I might even get the BE Micro CV if they are still available. After I check it out a bit more then I'm thinking of playing with the Verilog files to see what I can do if I had an instruction set optimized for my Tachyon VM, remember that Forth is actually the higher levels of that VM. I also don't see why the VM opcodes couldn't be used by a C compiler either, it's just another "CPU". So if I find some time I might look at writing a simple C compiler to do just that.
I'd like to catchup on a lot of these posts but I might not be able to in the short term but I would appreciate any tips in the meantime.
Comments
Sorry to hear about the eye trouble, that has to be frustrating in our business/hobby.
I have the P1 running on a Nano and a BE micro - I haven't tried my DE2 yet.
You can certainly hang a real EEPROM off of pins 28/29 - that works just like a real P1.
There is currently an issue with reset that it looks like pik33 may have solved - I haven't tested his patch yet but it looks hopeful.
Without the patch, it just doesn't reset reliably but a power cycle usually fixes that. If you are putting your code to RAM (F10) then it's just a hassle. If you're putting your code to an attached EEPROM, it can be hard to reprogram your EEPROM - you need to be quick between the power on and the F11 or it will just boot from the EEPROM.
The VM sounds like fun. I was thinking along those lines but I'm sure you will get much further, much faster than I ever do.
The instructions that I had really liked from the old P2 were the stack instructions and the SERIN/SEROUT. It would be fun to have a P1 with a real stack (in an AUXRAM area, maybe??).
Most of my stuff is running out of one cog so I might just play with hub access for a bit of fun, that should move it along for sure
But so many times I would code PASM and see possibilities with enhanced instructions as I have written assembly for scores and scores of different cores (it rhymes). So some simple tweaking first off should produce some nice results but there is also the I/O port OR'ing that I would like to address and see if I can also get it so that any low will pull a pin low which is far more common usage anyway.
I have an idea!!!
Now would be a good time to figure out how to fix your bad eye... you never know:) That sounds like a joke, but I am absolutely sincere. When we get to the P2, I am thinking about asking Ken to make this an open project.
When I first started out in practice, we hired the young, thoroughly intelligent son of our office manager. He was a little on the high strung end of the scale and ended up with what was called "a central serous"...
This is a stress related condition that happens to young people. Usually, watchful waiting and some predisone are all that are required, but occasionally, as happened to this very nice kid, other things happen and you end up with a hole in your central vision. They eye ends up looking just like it got hit by a soccer ball... different mechanism but very similar final result. The final result also resembles the end stages of macular degeneration.
What holds hope for these eyes is that the retina is usually quite alive and attached to it's moorings... in the same way that scrambled eyes remain attache to a frying pan.
The technical name for the kind of visual defect is "meta-morphorphopsia."... If you look at a piece of graph paper with a good eye... it looks like graph paper. When these eyes look at a piece of graph paper, the lines are jumbled up and there are tiny holes, where nothing is seen.
The fix would be to convolve the image to correspond to the retinal distortion and then project that image properly onto the retina... when I was trying to solve this, the technology available to me just wasn't adequate. The Prop2 will be adequate.
Let's not distract Chip too much:)
Rich