Doing some Quartus optimizations/removing settings...
overclocked
Posts: 80
I'm not an expert (just a hobby FPGA enthusiast) but interested and trying to compile the project.
I've tried working with the Propeller 1 project in Quartus to get it to build faster.
By removing settings and easing the timing/optimizations, the project builds in 1min23sec which is quite nice.
Comparing to the baseline release, here are some statistics:
BUILD
SIZE
BUILDTIME
TIMING
ORIGINAL
14863/22320 (67%)
3min22sec
103.34Mhz
MINE
15923/22320 (71%)
1min23sec
55.65Mhz
SIZE comment:
Well it got somewhat smaller but that not the point of my experiments.
BUILD TIME:
This is good stuff i think. For anyone trying out different settings and compiling/synthesizing this project lots of times, a removing 2/3 of the waiting can be nice but it will cost some logic.
TIMING comment:
The lower 55 Mhz clock is due to me giving it the 50 Mhz input clock and 80 Mhz on COG's that doesn't seem to understand the connection in the original project. So the COG's STILL manages 80 Mhz without problems and also the internal 160Mhz PLL clock is specified.
The original says 1000 Mhz (unconstrained) COG clocks and of course never reaches this. So by removing/easing some of the project settings and specifying the clocks more in depth, i think is key to building this nice project even faster.
NOTE:
Because I don't have any Nano or DE2-115 a can't test it yet so the actual working test will have to wait...
Comments?
I've tried working with the Propeller 1 project in Quartus to get it to build faster.
By removing settings and easing the timing/optimizations, the project builds in 1min23sec which is quite nice.
Comparing to the baseline release, here are some statistics:
BUILD
SIZE
BUILDTIME
TIMING
ORIGINAL
14863/22320 (67%)
3min22sec
103.34Mhz
MINE
15923/22320 (71%)
1min23sec
55.65Mhz
SIZE comment:
Well it got somewhat smaller but that not the point of my experiments.
BUILD TIME:
This is good stuff i think. For anyone trying out different settings and compiling/synthesizing this project lots of times, a removing 2/3 of the waiting can be nice but it will cost some logic.
TIMING comment:
The lower 55 Mhz clock is due to me giving it the 50 Mhz input clock and 80 Mhz on COG's that doesn't seem to understand the connection in the original project. So the COG's STILL manages 80 Mhz without problems and also the internal 160Mhz PLL clock is specified.
The original says 1000 Mhz (unconstrained) COG clocks and of course never reaches this. So by removing/easing some of the project settings and specifying the clocks more in depth, i think is key to building this nice project even faster.
NOTE:
Because I don't have any Nano or DE2-115 a can't test it yet so the actual working test will have to wait...
Comments?
Comments
These are now using different revisions within the same project to be able to switch between them.
I'm not 100% sure I've choose the correct type of inheritance between these but I can fix that later.
The differences are:
- Separate SDC-files with different clock constraints
- Different optimize settings in Quartus.
BUILD
RESOURCES
BUILDTIME
FMax/COGFMax
Default/Original
15,015/22,320 ( 67 % )
3:29
103 / 223
MinResource
14,527/22,320 ( 65 % )
1:51
60 / 163
FastCompile
15,923/22,320 ( 71 % )
1:13
61 / 129
MaximumPerformance
15,970/22,320 ( 72 % )
4:10
70 / 250
I'm glad you're exploring this. Having to wait for a compile is really annoying.
We certainly have been spoilt! I remember most compiles on the mini took ~3-4 hours with many taking well in excess of that.
At least the mini had multiprocessors (quite similar to the P1) so you could work on another program while compiling.