Porting the Prop1 to other FPGA
John A. Zoidberg
Posts: 514
Just checking in, I have only seen the Prop1 inside the featured FPGA boards like the DE0, but I believe that all of these can also reside in other FPGA brands like Xilinx and Actel.
I have another CycloneII board bought from Ebay, and I know the Prop1 is not gonna fit inside due to the smaller size. However, I know the number of cogs can be dropped to 4 or 2 for experimentation purposes.
I have learnt Verilog before and skimmed the code - and before I'm told to "read the Verilog codes" again, is it ok if someone can point me the approximate location in "hub.v" where I can drop the number of cogs from 8 to 4 or 2? I believe it's called "bus_sel" or something here.
Again, I have to print the whole codes out and study them in my free time. I'm a bit too excited to modify some of it for my work.
As for the other interfacing to the ports and etcetera, I can take it from there myself.
I have another CycloneII board bought from Ebay, and I know the Prop1 is not gonna fit inside due to the smaller size. However, I know the number of cogs can be dropped to 4 or 2 for experimentation purposes.
I have learnt Verilog before and skimmed the code - and before I'm told to "read the Verilog codes" again, is it ok if someone can point me the approximate location in "hub.v" where I can drop the number of cogs from 8 to 4 or 2? I believe it's called "bus_sel" or something here.
Again, I have to print the whole codes out and study them in my free time. I'm a bit too excited to modify some of it for my work.
As for the other interfacing to the ports and etcetera, I can take it from there myself.
Comments
for i 0 to 7 i++
That is where it is expanded to 8 iterations. I am unsure if you can just reduce the iterations or there are other things requiring changes too.
output reg [7:0] cog_ena,
output [7:0] ptr_w,
output [27:0] ptr_d,
output reg [7:0] cfg
);
========================================
// cogs
reg [7:0] cog_e;
wire cog_start = sys && ac[2:0] == 3'b010 && !(dc[3] && all);
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_e <= 8'b00000001;
else if (ena_bus && sys && ac[2:1] == 2'b01)
cog_e <= cog_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_ena <= 8'b0;
else if (ena_bus)
cog_ena <= cog_e & ~({8{cog_start}} & num_dcd);
assign ptr_w = {8{cog_start}} & num_dcd;
assign ptr_d = dc[31:4];
As I do not have a DE0, I'll open the files provided by Parallax inc. in the Quartus and look at the block diagram (if there is one) and then improvise from there.
I will drop the total cores (cogs) to 2 as a start first as I have other stuff to do at this moment.
Paul
Assuming LE's are created equal, your XC3S100E should fit one cog.
Two on an XC3S200
Four on an S500
I have those Xilinx FPGA's in my lab (mostly on SeeedStudio Papilio's), but sadly no time right now to try the Verilog on them.
http://www.seeedstudio.com/depot/Papilio-One-500K-p-811.html?cPath=6_10
I think the above might fit four cogs.
Please keep us updated - I for one am very interested in the results of your experiment.