What is the most suitable FPGA type... Cyclone V, Cyclone IV, Spartan 6, Spartan 3A ?

Cluso99 · 2014-08-08 19:47

I was surprised that the Cyclone V on the BeMicro CV compiled so poorly.

So, I am wondering what usage/speed can be obtained from the various FPGA formats.

If you compile the original posted P1 code for any FPGA, could you please post your results here so we can compare them?

jazzed · 2014-08-08 20:49

I don't have any Cyclone V results yet, but should have the BeMicro CV board by Monday night, so any Cyclone V results definitely interest me.

Here are the unmodified Cyclone IV E results.

My compile results for Chip's Terasic DE0-Nano package:

Flow Status    Successful - Fri Aug 08 17:04:30 2014
Quartus II 64-Bit Version    14.0.0 Build 200 06/17/2014 SJ Web Edition
Revision Name    top
Top-level Entity Name    top
Family    Cyclone IV E
Device    EP4CE22F17C6
Timing Models    Final
Total logic elements    14,707 / 22,320 ( 66 % )
Total combinational functions    13,363 / 22,320 ( 60 % )
Dedicated logic registers    5,430 / 22,320 ( 24 % )
Total registers    5430
Total pins    42 / 154 ( 27 % )
Total virtual pins    0
Total memory bits    524,288 / 608,256 ( 86 % )
Embedded Multiplier 9-bit elements    0 / 132 ( 0 % )
Total PLLs    1 / 4 ( 25 % )

My compile results for Chip's Terasic DE2-115 package:

Flow Status    Successful - Fri Aug 08 20:34:13 2014
Quartus II 64-Bit Version    14.0.0 Build 200 06/17/2014 SJ Web Edition
Revision Name    top
Top-level Entity Name    top
Family    Cyclone IV E
Device    EP4CE115F29C7
Timing Models    Final
Total logic elements    14,572 / 114,480 ( 13 % )
Total combinational functions    13,385 / 114,480 ( 12 % )
Dedicated logic registers    5,431 / 114,480 ( 5 % )
Total registers    5431
Total pins    42 / 529 ( 8 % )
Total virtual pins    0
Total memory bits    655,360 / 3,981,312 ( 16 % )
Embedded Multiplier 9-bit elements    0 / 532 ( 0 % )
Total PLLs    1 / 4 ( 25 % )

jmg · 2014-08-08 21:33

Interesting memory figures. First says uses 65536 Bytes, the other 81920 Bytes, and I think the Nano chip said has the Character ROM removed.
Reports a possible 76032 Bytes on the Nano, what is using the RAM ?

jazzed · 2014-08-08 21:47

Here are Cyclone V compile results built according to Chip's instructions.

Flow Status	Successful - Fri Aug 08 21:14:15 2014
Quartus II 64-Bit Version	14.0.0 Build 200 06/17/2014 SJ Web Edition
Revision Name	top
Top-level Entity Name	top
Family	Cyclone V
Device	5CEFA2F23C8
Timing Models	Final
Logic utilization (in ALMs)	8,522 / 9,430 ( 90 % )
Total registers	5746
Total pins	42 / 224 ( 19 % )
Total virtual pins	0
Total block memory bits	655,360 / 1,802,240 ( 36 % )
Total DSP Blocks	0 / 25 ( 0 % )
Total HSSI RX PCSs	0
Total HSSI PMA RX Deserializers	0
Total HSSI TX PCSs	0
Total HSSI PMA TX Serializers	0
Total PLLs	1 / 4 ( 25 % )
Total DLLs	0 / 4 ( 0 % )

jazzed · 2014-08-08 22:30

Hmm.

Maybe I can make a 384K Byte HUB RAM P1 on the DE2-115 board tomorrow (out of 440KB) ... in my dreams.

Someone knows how though. jmg?

Cluso99 · 2014-08-09 04:00

jazzed wrote: »

Hmm.

Maybe I can make a 384K Byte HUB RAM P1 on the DE2-115 board tomorrow (out of 440KB) ... in my dreams.

Someone knows how though. jmg?

Allocation is quite easy. Addressing it is another problem. At least you can see what is usable (configurable).

BTW Thanks for your compile results. Now we need someone to do the same for Spartan 3A and 6.

Cluso99 · 2014-08-09 04:40

For memory usage on DE0
8 * 2KB cogs + 32KB+16KB=48KB hub
Total 64KB = 512Kb = 524,288 bits

For memory usage on DE2
8 * 2KB cogs + 64KB hub
Total 80KB = 640Kb = 655,360 bits

On the DE0 we have 608,256 bits avail
608,256 b / 1024 = 594Kb = 74.25KB
74.25KB - (8 * 2KB cogs) = 58.25KB
So, 56KB hub might be available - so we should try 48KB hub ram and double map the last 2 * 8KB of ROM.
But to try it without generating a new ROM file, keep the 32KB hub ram, and add 2 * 8KB double mapped ram next, then the last 16KB of ROM.
This gives us 40KB hub ram with the 32-40KB also mapped as 40-48KB. The followed by the 16KB ROM.

On the DE2 we have 3,981,312 bits avail
3,981,312 b / 1024 = 3888Kb = 486KB
486KB - (8 * 2KB cogs) = 470KB
So we have ~470KB hub ram/rom available.

Bill Henning · 2014-08-09 07:07

Good plan Ray.

Re/ addressing - not much of an issue for RDxxxx / WRxxxx as they already theoretically can address a 32 bit address space.

For an interesting variant, I suggest:

512 long boot loader at byte address $0-$3FF (long addresses $0-$1FF)
ram for the rest
hubexec

jazzed · 2014-08-09 07:29

Bill Henning wrote: »

512 long boot loader at byte address $0-$3FF (long addresses $0-$1FF)

Stupid question time:

How can a bootloader be done that would keep all RAM free?

Bill Henning · 2014-08-09 07:49

No, I think that is a good question.

Basically, I was thinking of the first 512 longs in the hub being preset to be "ROM" (like on the P2) and hold just a cog image, loaded into cog0 and run at bootup.

Then that cog would be responsible for loading from eeprom/flash.

We would have a choice of keeping the boot rom mapped in, losing the first 512 longs from being used as ram, or the boot cog could flip a bit, and map ram back there.

From P2 discussions, if the first 512 longs in the memory map were mapped as cog addresses, it does not matter if they are not ram.

Or the bootloader could be in high memory, or not even present in the memory space - cog0 could be loaded from a "hidden" rom on startup.

Many choices to explore!

jazzed wrote: »

Stupid question time:

How can a bootloader be done that would keep all RAM free?

pik33 · 2014-08-09 10:12

jazzed wrote: »

Stupid question time:

How can a bootloader be done that would keep all RAM free?

Simply add a switchable (with mux, for example) rom block with bootloader which will connect to the Propeller after reset and then disconnect itself after doing its work.

Or add a circuit which, after reset, will preload bootloader to RAM.

jazzed · 2014-08-09 12:19

pik33 wrote: »

Simply add a switchable (with mux, for example) rom block with bootloader which will connect to the Propeller after reset and then disconnect itself after doing its work.

Or add a circuit which, after reset, will preload bootloader to RAM.

Great! Sounds perfect. No memory pot-holes!

pedward · 2014-08-09 14:04

pik33 wrote: »

Simply add a switchable (with mux, for example) rom block with bootloader which will connect to the Propeller after reset and then disconnect itself after doing its work.

Or add a circuit which, after reset, will preload bootloader to RAM.

Somebody spent too much time programming the MC68000

Cluso99 · 2014-08-09 15:44

Hey guys,
Can we keep this thread on topic.
Great discussions, but they would be better in their own thread. Thanks

rogloh · 2014-08-09 18:08

Cluso99 wrote: »

For memory usage on DE0
8 * 2KB cogs + 32KB+16KB=48KB hub
Total 64KB = 512Kb = 524,288 bits

For memory usage on DE2
8 * 2KB cogs + 64KB hub
Total 80KB = 640Kb = 655,360 bits

On the DE0 we have 608,256 bits avail
608,256 b / 1024 = 594Kb = 74.25KB
74.25KB - (8 * 2KB cogs) = 58.25KB
So, 56KB hub might be available - so we should try 48KB hub ram and double map the last 2 * 8KB of ROM.
But to try it without generating a new ROM file, keep the 32KB hub ram, and add 2 * 8KB double mapped ram next, then the last 16KB of ROM.
This gives us 40KB hub ram with the 32-40KB also mapped as 40-48KB. The followed by the 16KB ROM.

On the DE2 we have 3,981,312 bits avail
3,981,312 b / 1024 = 3888Kb = 486KB
486KB - (8 * 2KB cogs) = 470KB
So we have ~470KB hub ram/rom available.

Cluso,

It's been a while since I designed a few things with FPGAs (ok this will start to show my age, early '90s using XC3000 family Xilinx devices and with schematic capture only - not HDLs back then) but I am not sure that you can easily divide FPGA memory that finely. In general the available memory blocks are 9 bit wide so you only get 8/9ths of the capacity when storing byte wide quantities to the RAM. The extra bit in each byte, or bits when parallel widened > 8 bits, tends to become useful for other purposes such as fifo flags/frame delimiters, data validity/parity bits, etc but not to store the data itself. Perhaps you could but I suspect it would ugly real fast and start to involve multiple accesses per byte. So when considering this, I believe the DE-0 nano would effectively have about 66kB SRAM to play with when you lose the 9th bit.

rogloh

Cluso99 · 2014-08-09 19:44

ragloh,
Yes, there will be some loss of use in there.
I have just downloaded the latest Quartus so when I get home I can try a few things out.

I too designed a few boards with Xilinx parts in the 90's. But I hand routed my designs for maximum speed. Lucky they were only small designs. One was a bus interface to a mini.

jazzed · 2014-08-09 22:12

What's off topic Ray?

I'm happy to remove any of my postings that you seriously deem off topic, and I assume that others may remove theirs also.

pik33 · 2014-08-09 22:52

pedward wrote: »

Somebody spent too much time programming the MC68000

Connecting 68000 to the Propeller may give us an interesting results

Cluso99 · 2014-08-10 00:51

jazzed wrote: »

What's off topic Ray?

I'm happy to remove any of my postings that you seriously deem off topic, and I assume that others may remove theirs also.

No, I'd rather just keep this for discussing the suitability and comparisons of the FPGAs and have a new topic for discussing memory layouts. That way I (and others) can find it easily. I normally wouldn't think to look in this thread for those sort of discussions.

Cluso99 · 2014-08-10 03:40

Here is the results for Quartus 64bit v14.0.0.200 for the DE0-Nano (original files unchanged)...

Flow Status    Successful - Sun Aug 10 20:07:15 2014
Quartus II 64-Bit Version    14.0.0 Build 200 06/17/2014 SJ Web Edition
Revision Name    top
Top-level Entity Name    top
Family    Cyclone IV E
Device    EP4CE22F17C6
Timing Models    Final
Total logic elements    14,707 / 22,320 ( 66 % )
Total combinational functions    13,363 / 22,320 ( 60 % )
Dedicated logic registers    5,430 / 22,320 ( 24 % )
Total registers    5430
Total pins    42 / 154 ( 27 % )
Total virtual pins    0
Total memory bits    524,288 / 608,256 ( 86 % )
Embedded Multiplier 9-bit elements    0 / 132 ( 0 % )
Total PLLs    1 / 4 ( 25 % )

And here is the log. Note the warnings - unsure what some of them mean.
[code]
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
Info: Processing started: Sun Aug 10 19:57:22 2014
Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
Info: Processing started: Sun Aug 10 19:57:22 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (12125): Using design file top.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: top
Info (12023): Found entity 1: top
Info (12127): Elaborating entity "top" for the top level hierarchy
Info (12128): Elaborating entity "altpll" for hierarchy "altpll:pll"
Info (12130): Elaborated megafunction instantiation "altpll:pll"
Info (12133): Instantiated megafunction "altpll:pll" with the following parameter:
Info (12134): Parameter "clk0_divide_by" = "5"
Info (12134): Parameter "clk0_multiply_by" = "16"
Info (12134): Parameter "inclk0_input_frequency" = "20000"
Info (12134): Parameter "operation_mode" = "normal"
Info (12134): Parameter "pll_type" = "enhanced"
Info (12134): Parameter "width_clock" = "6"
Info (12134): Parameter "width_phasecounterselect" = "4"
Info (12134): Parameter "clk0_divide_by" = "5"
Info (12134): Parameter "clk0_multiply_by" = "16"
Info (12134): Parameter "inclk0_input_frequency" = "20000"
Info (12134): Parameter "operation_mode" = "normal"
Info (12134): Parameter "pll_type" = "enhanced"
Info (12134): Parameter "width_clock" = "6"
Info (12134): Parameter "width_phasecounterselect" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_ejp.tdf
Info (12023): Found entity 1: altpll_ejp
Info (12023): Found entity 1: altpll_ejp
Info (12128): Elaborating entity "altpll_ejp" for hierarchy "altpll:pll|altpll_ejp:auto_generated"
Warning (12125): Using design file tim.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: tim
Info (12023): Found entity 1: tim
Info (12128): Elaborating entity "tim" for hierarchy "tim:clkgen"
Warning (12125): Using design file dig.v, which is not specified as a design file for the current project, but contains definitions for 8 design units and 8 entities in project
Info (12023): Found entity 1: cog_ram
Info (12023): Found entity 2: cog_alu
Info (12023): Found entity 3: cog_ctr
Info (12023): Found entity 4: cog_vid
Info (12023): Found entity 5: cog
Info (12023): Found entity 6: hub_mem
Info (12023): Found entity 7: hub
Info (12023): Found entity 8: dig
Info (12023): Found entity 1: cog_ram
Info (12023): Found entity 2: cog_alu
Info (12023): Found entity 3: cog_ctr
Info (12023): Found entity 4: cog_vid
Info (12023): Found entity 5: cog
Info (12023): Found entity 6: hub_mem
Info (12023): Found entity 7: hub
Info (12023): Found entity 8: dig
Info (12128): Elaborating entity "dig" for hierarchy "dig:core"
Info (12128): Elaborating entity "cog" for hierarchy "dig:core|cog:coggen[0].cog_"
Info (12128): Elaborating entity "cog_ram" for hierarchy "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_"
Warning (276027): Inferred dual-clock RAM node "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_|altsyncram:r[0][31]__1" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
Info (19000): Inferred 1 megafunctions from design logic
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_|altsyncram:r[0][31]__1"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 9
Info (286033): Parameter NUMWORDS_A set to 512
Info (286033): Parameter WIDTH_B set to 32
Info (286033): Parameter WIDTHAD_B set to 9
Info (286033): Parameter NUMWORDS_B set to 512
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK1
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_|altsyncram:r[0][31]__1"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 9
Info (286033): Parameter NUMWORDS_A set to 512
Info (286033): Parameter WIDTH_B set to 32
Info (286033): Parameter WIDTHAD_B set to 9
Info (286033): Parameter NUMWORDS_B set to 512
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK1
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 9
Info (286033): Parameter NUMWORDS_A set to 512
Info (286033): Parameter WIDTH_B set to 32
Info (286033): Parameter WIDTHAD_B set to 9
Info (286033): Parameter NUMWORDS_B set to 512
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK1
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (12128): Elaborating entity "altsyncram" for hierarchy "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_|altsyncram:r[0][31]__1"
Info (12130): Elaborated megafunction instantiation "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_|altsyncram:r[0][31]__1"
Info (12133): Instantiated megafunction "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_|altsyncram:r[0][31]__1" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "32"
Info (12134): Parameter "WIDTHAD_A" = "9"
Info (12134): Parameter "NUMWORDS_A" = "512"
Info (12134): Parameter "WIDTH_B" = "32"
Info (12134): Parameter "WIDTHAD_B" = "9"
Info (12134): Parameter "NUMWORDS_B" = "512"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "32"
Info (12134): Parameter "WIDTHAD_A" = "9"
Info (12134): Parameter "NUMWORDS_A" = "512"
Info (12134): Parameter "WIDTH_B" = "32"
Info (12134): Parameter "WIDTHAD_B" = "9"
Info (12134): Parameter "NUMWORDS_B" = "512"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_isd1.tdf
Info (12023): Found entity 1: altsyncram_isd1
Info (12023): Found entity 1: altsyncram_isd1
Info (12128): Elaborating entity "altsyncram_isd1" for hierarchy "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_|altsyncram:r[0][31]__1|altsyncram_isd1:auto_generated"
Info (12128): Elaborating entity "cog_ctr" for hierarchy "dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra"
Info (12128): Elaborating entity "cog_vid" for hierarchy "dig:core|cog:coggen[0].cog_|cog_vid:cog_vid_"
Info (12128): Elaborating entity "cog_alu" for hierarchy "dig:core|cog:coggen[0].cog_|cog_alu:cog_alu_"
Info (12128): Elaborating entity "hub" for hierarchy "dig:core|hub:hub_"
Info (12128): Elaborating entity "hub_mem" for hierarchy "dig:core|hub:hub_|hub_mem:hub_mem_"
Warning (10858): Verilog HDL warning at hub_mem.v(85): object rom_low used but never assigned
Warning (10036): Verilog HDL or VHDL warning at hub_mem.v(87): object "rom_low_q" assigned a value but never read
Warning (10858): Verilog HDL warning at hub_mem.v(96): object rom_high used but never assigned
Warning (19016): Clock multiplexers are found and protected
Warning (19017): Found clock multiplexer dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|Mux6
Warning (19017): Found clock multiplexer dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|Mux6
Warning (19016): Clock multiplexers are found and protected
Warning (19017): Found clock multiplexer tim:clkgen|clk_pll~2
Warning (19017): Found clock multiplexer tim:clkgen|clk_pll~2
Warning (276020): Inferred RAM node "dig:core|hub:hub_|hub_mem:hub_mem_|ram0_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "dig:core|hub:hub_|hub_mem:hub_mem_|ram3_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "dig:core|hub:hub_|hub_mem:hub_mem_|ram2_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "dig:core|hub:hub_|hub_mem:hub_mem_|ram1_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Info (19000): Inferred 5 megafunctions from design logic
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|rom_high_rtl_0"
Info (286033): Parameter OPERATION_MODE set to ROM
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 12
Info (286033): Parameter NUMWORDS_A set to 4096
Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_ACLR_A set to NONE
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to hub_rom_high.hex
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|ram0_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|ram3_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|ram2_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|ram1_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|rom_high_rtl_0"
Info (286033): Parameter OPERATION_MODE set to ROM
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 12
Info (286033): Parameter NUMWORDS_A set to 4096
Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_ACLR_A set to NONE
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to hub_rom_high.hex
Info (286033): Parameter OPERATION_MODE set to ROM
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 12
Info (286033): Parameter NUMWORDS_A set to 4096
Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_ACLR_A set to NONE
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to hub_rom_high.hex
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|ram0_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|ram3_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|ram2_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (276029): Inferred altsyncram megafunction from the following design logic: "dig:core|hub:hub_|hub_mem:hub_mem_|ram1_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 13
Info (286033): Parameter NUMWORDS_A set to 8192
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 13
Info (286033): Parameter NUMWORDS_B set to 8192
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (12130): Elaborated megafunction instantiation "dig:core|hub:hub_|hub_mem:hub_mem_|altsyncram:rom_high_rtl_0"
Info (12133): Instantiated megafunction "dig:core|hub:hub_|hub_mem:hub_mem_|altsyncram:rom_high_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "ROM"
Info (12134): Parameter "WIDTH_A" = "32"
Info (12134): Parameter "WIDTHAD_A" = "12"
Info (12134): Parameter "NUMWORDS_A" = "4096"
Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "INIT_FILE" = "hub_rom_high.hex"
Info (12134): Parameter "OPERATION_MODE" = "ROM"
Info (12134): Parameter "WIDTH_A" = "32"
Info (12134): Parameter "WIDTHAD_A" = "12"
Info (12134): Parameter "NUMWORDS_A" = "4096"
Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "INIT_FILE" = "hub_rom_high.hex"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_0u51.tdf
Info (12023): Found entity 1: altsyncram_0u51
Info (12023): Found entity 1: altsyncram_0u51
Warning (113015): Width of data items in "hub_rom_high.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 512 warnings, reporting 10
Warning (113009): Data at line (1) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (2) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (3) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (4) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (5) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (6) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (7) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (8) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (9) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (10) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (1) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (2) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (3) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (4) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (5) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (6) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (7) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (8) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (9) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Warning (113009): Data at line (10) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Info (12130): Elaborated megafunction instantiation "dig:core|hub:hub_|hub_mem:hub_mem_|altsyncram:ram0_rtl_0"
Info (12133): Instantiated megafunction "dig:core|hub:hub_|hub_mem:hub_mem_|altsyncram:ram0_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "13"
Info (12134): Parameter "NUMWORDS_A" = "8192"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "13"
Info (12134): Parameter "NUMWORDS_B" = "8192"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "13"
Info (12134): Parameter "NUMWORDS_A" = "8192"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "13"
Info (12134): Parameter "NUMWORDS_B" = "8192"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nii1.tdf
Info (12023): Found entity 1: altsyncram_nii1
Info (12023): Found entity 1: altsyncram_nii1
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 16903 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 8 output pins
Info (21060): Implemented 32 bidirectional pins
Info (21061): Implemented 16540 logic cells
Info (21064): Implemented 320 RAM segments
Info (21065): Implemented 1 PLLs
Info (21058): Implemented 2 input pins
Info (21059): Implemented 8 output pins
Info (21060): Implemented 32 bidirectional pins
Info (21061): Implemented 16540 logic cells
Info (21064): Implemented 320 RAM segments
Info (21065): Implemented 1 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 34 warnings
Info: Peak virtual memory: 829 megabytes
Info: Processing ended: Sun Aug 10 19:59:37 2014
Info: Elapsed time: 00:02:15
Info: Total CPU time (on all processors): 00:02:02
Info: Peak virtual memory: 829 megabytes
Info: Processing ended: Sun Aug 10 19:59:37 2014
Info: Elapsed time: 00:02:15
Info: Total CPU time (on all processors): 00:02:02
Info: *******************************************************************
Info: Running Quartus II 64-Bit Fitter
Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
Info: Processing started: Sun Aug 10 19:59:40 2014
Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
Info: Processing started: Sun Aug 10 19:59:40 2014
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off top -c top
Info: qfit2_default_script.tcl version: #1
Info: Project = top
Info: Revision = top
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EP4CE22F17C6 for design "top"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (15535): Implemented PLL "altpll:pll|altpll_ejp:auto_generated|pll1" as Cyclone IV E PLL type
Info (15099): Implementing clock multiplication of 16, clock division of 5, and phase shift of 0 degrees (0 ps) for altpll:pll|altpll_ejp:auto_generated|clk[0] port
Info (15099): Implementing clock multiplication of 16, clock division of 5, and phase shift of 0 degrees (0 ps) for altpll:pll|altpll_ejp:auto_generated|clk[0] port
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EP4CE10F17C6 is compatible
Info (176445): Device EP4CE6F17C6 is compatible
Info (176445): Device EP4CE15F17C6 is compatible
Info (176445): Device EP4CE10F17C6 is compatible
Info (176445): Device EP4CE6F17C6 is compatible
Info (176445): Device EP4CE15F17C6 is compatible
Info (169124): Fitter converted 4 user pins into dedicated programming pins
Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1
Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1
Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained generated clocks found in the design
Info (332144): No user constrained base clocks found in the design
Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.
Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~0 from: datac to: combout
Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~1 from: datac to: combout
Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~3 from: datac to: combout
Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~4 from: datac to: combout
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (176353): Automatically promoted node altpll:pll|altpll_ejp:auto_generated|clk[0] (placed in counter C0 of PLL_4)
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18
Info (176353): Automatically promoted node tim:clkgen|divide[12]
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
Info (176357): Destination node tim:clkgen|divide[12]~37
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_vid:cog_vid_|vid[30]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_vid:cog_vid_|vid[29]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[24]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[25]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_vid:cog_vid_|vid[30]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_vid:cog_vid_|vid[29]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[24]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[25]
Info (176357): Destination node dig:core|cog:coggen[2].cog_|cog_vid:cog_vid_|vid[30]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
Info (176357): Destination node tim:clkgen|divide[12]~37
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_vid:cog_vid_|vid[30]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_vid:cog_vid_|vid[29]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[24]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[25]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_vid:cog_vid_|vid[30]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_vid:cog_vid_|vid[29]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[24]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[25]
Info (176357): Destination node dig:core|cog:coggen[2].cog_|cog_vid:cog_vid_|vid[30]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176357): Destination node tim:clkgen|divide[12]~37
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_vid:cog_vid_|vid[30]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_vid:cog_vid_|vid[29]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[24]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[25]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_vid:cog_vid_|vid[30]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_vid:cog_vid_|vid[29]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[24]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[25]
Info (176357): Destination node dig:core|cog:coggen[2].cog_|cog_vid:cog_vid_|vid[30]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176353): Automatically promoted node tim:clkgen|clk_pll
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[35]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[34]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[33]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[32]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[31]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[30]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[29]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[28]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|pll_fake[35]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|pll_fake[34]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[35]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[34]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[33]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[32]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[31]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[30]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[29]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[28]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|pll_fake[35]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|pll_fake[34]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[35]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[34]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[33]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[32]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[31]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[30]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[29]
Info (176357): Destination node dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|pll_fake[28]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|pll_fake[35]
Info (176357): Destination node dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|pll_fake[34]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176353): Automatically promoted node dig:core|cog:coggen[0].cog_|cog_vid:cog_vid_|vclk
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node dig:core|cog:coggen[1].cog_|cog_vid:cog_vid_|vclk
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node dig:core|cog:coggen[2].cog_|cog_vid:cog_vid_|vclk
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node dig:core|cog:coggen[3].cog_|cog_vid:cog_vid_|vclk
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node dig:core|cog:coggen[4].cog_|cog_vid:cog_vid_|vclk
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node dig:core|cog:coggen[5].cog_|cog_vid:cog_vid_|vclk
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node dig:core|cog:coggen[6].cog_|cog_vid:cog_vid_|vclk
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node dig:core|cog:coggen[7].cog_|cog_vid:cog_vid_|vclk
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node nres
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
Info (176357): Destination node dig:core|cnt[2]
Info (176357): Destination node dig:core|cnt[1]
Info (176357): Destination node dig:core|cnt[3]
Info (176357): Destination node dig:core|cnt[4]
Info (176357): Destination node dig:core|cnt[5]
Info (176357): Destination node dig:core|cnt[6]
Info (176357): Destination node dig:core|cnt[7]
Info (176357): Destination node dig:core|cnt[8]
Info (176357): Destination node dig:core|cnt[9]
Info (176357): Destination node dig:core|cnt[10]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
Info (176357): Destination node dig:core|cnt[2]
Info (176357): Destination node dig:core|cnt[1]
Info (176357): Destination node dig:core|cnt[3]
Info (176357): Destination node dig:core|cnt[4]
Info (176357): Destination node dig:core|cnt[5]
Info (176357): Destination node dig:core|cnt[6]
Info (176357): Destination node dig:core|cnt[7]
Info (176357): Destination node dig:core|cnt[8]
Info (176357): Destination node dig:core|cnt[9]
Info (176357): Destination node dig:core|cnt[10]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176357): Destination node dig:core|cnt[2]
Info (176357): Destination node dig:core|cnt[1]
Info (176357): Destination node dig:core|cnt[3]
Info (176357): Destination node dig:core|cnt[4]
Info (176357): Destination node dig:core|cnt[5]
Info (176357): Destination node dig:core|cnt[6]
Info (176357): Destination node dig:core|cnt[7]
Info (176357): Destination node dig:core|cnt[8]
Info (176357): Destination node dig:core|cnt[9]
Info (176357): Destination node dig:core|cnt[10]
Info (176358): Non-global destination nodes limited to 10 nodes
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Extra Info (176219): No registers were packed into other blocks
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:19
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:25
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:03:16
Info (170193): Fitter routing operations beginning
Info (170089): 7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 31% of the available device resources
Info (170196): Router estimated peak interconnect usage is 48% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22
Info (170196): Router estimated peak interconnect usage is 48% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22
Info (170194): Fitter routing operations ending: elapsed time is 00:02:26
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170201): Optimizations that may affect the design's routability were skipped
Info (11888): Total time spent on timing analysis during the Fitter is 51.84 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:20
Warning (169177): 34 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
Info (169178): Pin io[0] uses I/O standard 3.3-V LVCMOS at J14
Info (169178): Pin io[1] uses I/O standard 3.3-V LVCMOS at J13
Info (169178): Pin io[2] uses I/O standard 3.3-V LVCMOS at K15
Info (169178): Pin io[3] uses I/O standard 3.3-V LVCMOS at J16
Info (169178): Pin io[4] uses I/O standard 3.3-V LVCMOS at L13
Info (169178): Pin io[5] uses I/O standard 3.3-V LVCMOS at M10
Info (169178): Pin io[6] uses I/O standard 3.3-V LVCMOS at N14
Info (169178): Pin io[7] uses I/O standard 3.3-V LVCMOS at L14
Info (169178): Pin io[8] uses I/O standard 3.3-V LVCMOS at P14
Info (169178): Pin io[9] uses I/O standard 3.3-V LVCMOS at N15
Info (169178): Pin io[10] uses I/O standard 3.3-V LVCMOS at N16
Info (169178): Pin io[11] uses I/O standard 3.3-V LVCMOS at R14
Info (169178): Pin io[12] uses I/O standard 3.3-V LVCMOS at P16
Info (169178): Pin io[13] uses I/O standard 3.3-V LVCMOS at P15
Info (169178): Pin io[14] uses I/O standard 3.3-V LVCMOS at L15
Info (169178): Pin io[15] uses I/O standard 3.3-V LVCMOS at R16
Info (169178): Pin io[16] uses I/O standard 3.3-V LVCMOS at K16
Info (169178): Pin io[17] uses I/O standard 3.3-V LVCMOS at L16
Info (169178): Pin io[18] uses I/O standard 3.3-V LVCMOS at N11
Info (169178): Pin io[19] uses I/O standard 3.3-V LVCMOS at N9
Info (169178): Pin io[20] uses I/O standard 3.3-V LVCMOS at P9
Info (169178): Pin io[21] uses I/O standard 3.3-V LVCMOS at N12
Info (169178): Pin io[22] uses I/O standard 3.3-V LVCMOS at R10
Info (169178): Pin io[23] uses I/O standard 3.3-V LVCMOS at P11
Info (169178): Pin io[24] uses I/O standard 3.3-V LVCMOS at R11
Info (169178): Pin io[25] uses I/O standard 3.3-V LVCMOS at T10
Info (169178): Pin io[26] uses I/O standard 3.3-V LVCMOS at T11
Info (169178): Pin io[27] uses I/O standard 3.3-V LVCMOS at R12
Info (169178): Pin io[28] uses I/O standard 3.3-V LVCMOS at T12
Info (169178): Pin io[29] uses I/O standard 3.3-V LVCMOS at R13
Info (169178): Pin io[30] uses I/O standard 3.3-V LVCMOS at B11
Info (169178): Pin io[31] uses I/O standard 3.3-V LVCMOS at E10
Info (169178): Pin inp_resn uses I/O standard 3.3-V LVCMOS at D9
Info (169178): Pin clock_50 uses I/O standard 3.3-V LVCMOS at R8
Info (169178): Pin io[0] uses I/O standard 3.3-V LVCMOS at J14
Info (169178): Pin io[1] uses I/O standard 3.3-V LVCMOS at J13
Info (169178): Pin io[2] uses I/O standard 3.3-V LVCMOS at K15
Info (169178): Pin io[3] uses I/O standard 3.3-V LVCMOS at J16
Info (169178): Pin io[4] uses I/O standard 3.3-V LVCMOS at L13
Info (169178): Pin io[5] uses I/O standard 3.3-V LVCMOS at M10
Info (169178): Pin io[6] uses I/O standard 3.3-V LVCMOS at N14
Info (169178): Pin io[7] uses I/O standard 3.3-V LVCMOS at L14
Info (169178): Pin io[8] uses I/O standard 3.3-V LVCMOS at P14
Info (169178): Pin io[9] uses I/O standard 3.3-V LVCMOS at N15
Info (169178): Pin io[10] uses I/O standard 3.3-V LVCMOS at N16
Info (169178): Pin io[11] uses I/O standard 3.3-V LVCMOS at R14
Info (169178): Pin io[12] uses I/O standard 3.3-V LVCMOS at P16
Info (169178): Pin io[13] uses I/O standard 3.3-V LVCMOS at P15
Info (169178): Pin io[14] uses I/O standard 3.3-V LVCMOS at L15
Info (169178): Pin io[15] uses I/O standard 3.3-V LVCMOS at R16
Info (169178): Pin io[16] uses I/O standard 3.3-V LVCMOS at K16
Info (169178): Pin io[17] uses I/O standard 3.3-V LVCMOS at L16
Info (169178): Pin io[18] uses I/O standard 3.3-V LVCMOS at N11
Info (169178): Pin io[19] uses I/O standard 3.3-V LVCMOS at N9
Info (169178): Pin io[20] uses I/O standard 3.3-V LVCMOS at P9
Info (169178): Pin io[21] uses I/O standard 3.3-V LVCMOS at N12
Info (169178): Pin io[22] uses I/O standard 3.3-V LVCMOS at R10
Info (169178): Pin io[23] uses I/O standard 3.3-V LVCMOS at P11
Info (169178): Pin io[24] uses I/O standard 3.3-V LVCMOS at R11
Info (169178): Pin io[25] uses I/O standard 3.3-V LVCMOS at T10
Info (169178): Pin io[26] uses I/O standard 3.3-V LVCMOS at T11
Info (169178): Pin io[27] uses I/O standard 3.3-V LVCMOS at R12
Info (169178): Pin io[28] uses I/O standard 3.3-V LVCMOS at T12
Info (169178): Pin io[29] uses I/O standard 3.3-V LVCMOS at R13
Info (169178): Pin io[30] uses I/O standard 3.3-V LVCMOS at B11
Info (169178): Pin io[31] uses I/O standard 3.3-V LVCMOS at E10
Info (169178): Pin inp_resn uses I/O standard 3.3-V LVCMOS at D9
Info (169178): Pin clock_50 uses I/O standard 3.3-V LVCMOS at R8
Info (144001): Generated suppressed messages file C:/altera/14.0/P8X32A_DE0_Nano/top.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 970 megabytes
Info: Processing ended: Sun Aug 10 20:07:04 2014
Info: Elapsed time: 00:07:24
Info: Total CPU time (on all processors): 00:07:11
Info: Peak virtual memory: 970 megabytes
Info: Processing ended: Sun Aug 10 20:07:04 2014
Info: Elapsed time: 00:07:24
Info: Total CPU time (on all processors): 00:07:11
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
Info: Processing started: Sun Aug 10 20:07:09 2014
Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
Info: Processing started: Sun Aug 10 20:07:09 2014
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off top -c top
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 546 megabytes
Info: Processing ended: Sun Aug 10 20:07:15 2014
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
Info: Peak vir

Cluso99 · 2014-08-10 03:42

...continued from previous post...

Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
    Info: Processing started: Sun Aug 10 20:07:18 2014
    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
    Info: Processing started: Sun Aug 10 20:07:18 2014
Info: Command: quartus_sta top -c top
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not  found: 'top.sdc'. A Synopsys Design Constraints File is required by the  TimeQuest Timing Analyzer to get proper timing constraints. Without it,  the Compiler will not properly optimize the design.
Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info (332110): Deriving PLL clocks
    Info (332110): create_clock -period 20.000 -waveform {0.000 10.000} -name clock_50 clock_50
    Info (332110): create_generated_clock -source  {pll|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 16  -duty_cycle 50.00 -name {pll|auto_generated|pll1|clk[0]}  {pll|auto_generated|pll1|clk[0]}
    Info (332110): create_clock -period 20.000 -waveform {0.000 10.000} -name clock_50 clock_50
    Info (332110): create_generated_clock -source  {pll|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 16  -duty_cycle 50.00 -name {pll|auto_generated|pll1|clk[0]}  {pll|auto_generated|pll1|clk[0]}
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name tim:clkgen|divide[12] tim:clkgen|divide[12]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name tim:clkgen|divide[12] tim:clkgen|divide[12]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23]
    Info (332105): create_clock -period 1.000 -name  dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23]  dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23]
Info (332097): The following timing edges are non-unate.  TimeQuest will  assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~4  from: datab  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~0  from: datab  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~3  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~0  from: dataa  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~4  from: datab  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~0  from: datab  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~3  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~0  from: dataa  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~4  from: datac  to: combout
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report  Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    Info (11105): For recommendations on closing timing, run Report  Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -8.537
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -8.537          -23234.750 tim:clkgen|divide[12] 
    Info (332119):    -4.667           -2083.642 pll|auto_generated|pll1|clk[0] 
    Info (332119):    -3.330            -323.556 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.997            -259.837 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.911            -262.853 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.795            -253.199 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.793            -264.611 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.745            -256.572 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.636            -251.204 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.545            -239.920 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -8.537          -23234.750 tim:clkgen|divide[12] 
    Info (332119):    -4.667           -2083.642 pll|auto_generated|pll1|clk[0] 
    Info (332119):    -3.330            -323.556 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.997            -259.837 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.911            -262.853 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.795            -253.199 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.793            -264.611 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.745            -256.572 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.636            -251.204 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.545            -239.920 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
Info (332146): Worst-case hold slack is -1.468
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.468             -44.627 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.416             -40.489 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.397             -10.477 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.096             -31.143 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.859             -74.247 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.815             -73.552 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.358             -23.961 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.084              -1.375 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.273               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     0.311               0.000 tim:clkgen|divide[12] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.468             -44.627 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.416             -40.489 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.397             -10.477 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.096             -31.143 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.859             -74.247 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.815             -73.552 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.358             -23.961 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.084              -1.375 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.273               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     0.311               0.000 tim:clkgen|divide[12] 
Info (332146): Worst-case recovery slack is -3.058
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.058           -1405.020 tim:clkgen|divide[12] 
    Info (332119):    -0.562              -0.562 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.255              -0.255 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.189               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.297               0.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.335               0.000 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.511               0.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.694               0.000 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.765               0.000 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.058           -1405.020 tim:clkgen|divide[12] 
    Info (332119):    -0.562              -0.562 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.255              -0.255 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.189               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.297               0.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.335               0.000 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.511               0.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.694               0.000 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.765               0.000 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
Info (332146): Worst-case removal slack is -0.934
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.934              -0.934 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.773              -0.773 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.659              -0.659 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.631              -0.631 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.371              -0.371 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.215              -0.215 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.192              -0.192 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.256               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     1.377               0.000 tim:clkgen|divide[12] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.934              -0.934 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.773              -0.773 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.659              -0.659 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.631              -0.631 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.371              -0.371 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.215              -0.215 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.192              -0.192 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.256               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     1.377               0.000 tim:clkgen|divide[12] 
Info (332146): Worst-case minimum pulse width slack is -2.174
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.174           -4392.192 tim:clkgen|divide[12] 
    Info (332119):    -1.000            -427.501 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -183.094 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -154.899 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -147.266 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -139.811 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -132.045 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -131.174 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -121.784 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     2.818               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     9.747               0.000 clock_50 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.174           -4392.192 tim:clkgen|divide[12] 
    Info (332119):    -1.000            -427.501 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -183.094 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -154.899 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -147.266 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -139.811 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -132.045 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -131.174 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -121.784 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     2.818               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     9.747               0.000 clock_50 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332097): The following timing edges are non-unate.  TimeQuest will  assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~4  from: datab  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~0  from: datab  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~3  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~0  from: dataa  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~4  from: datab  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~0  from: datab  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~3  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~0  from: dataa  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~4  from: datac  to: combout
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report  Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    Info (11105): For recommendations on closing timing, run Report  Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -7.664
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -7.664          -20472.285 tim:clkgen|divide[12] 
    Info (332119):    -4.024           -1834.901 pll|auto_generated|pll1|clk[0] 
    Info (332119):    -2.921            -281.084 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.625            -223.620 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.554            -227.158 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.444            -216.626 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.440            -227.736 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.392            -221.505 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.312            -216.698 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.212            -205.061 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -7.664          -20472.285 tim:clkgen|divide[12] 
    Info (332119):    -4.024           -1834.901 pll|auto_generated|pll1|clk[0] 
    Info (332119):    -2.921            -281.084 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.625            -223.620 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.554            -227.158 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.444            -216.626 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.440            -227.736 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.392            -221.505 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.312            -216.698 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -2.212            -205.061 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
Info (332146): Worst-case hold slack is -1.248
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.248             -29.995 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.223             -28.035 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.196              -3.585 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.915             -18.520 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.712             -58.548 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.664             -58.602 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.267             -16.414 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.016               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.182               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     0.297               0.000 tim:clkgen|divide[12] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.248             -29.995 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.223             -28.035 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.196              -3.585 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.915             -18.520 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.712             -58.548 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.664             -58.602 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.267             -16.414 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.016               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.182               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     0.297               0.000 tim:clkgen|divide[12] 
Info (332146): Worst-case recovery slack is -2.618
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.618           -1160.107 tim:clkgen|divide[12] 
    Info (332119):    -0.442              -0.442 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.223              -0.223 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.262               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.318               0.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.350               0.000 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.503               0.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.666               0.000 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.747               0.000 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.618           -1160.107 tim:clkgen|divide[12] 
    Info (332119):    -0.442              -0.442 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.223              -0.223 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.262               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.318               0.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.350               0.000 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.503               0.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.666               0.000 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.747               0.000 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
Info (332146): Worst-case removal slack is -0.786
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.786              -0.786 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.615              -0.615 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.515              -0.515 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.494              -0.494 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.260              -0.260 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.121              -0.121 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.114              -0.114 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.319               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     1.258               0.000 tim:clkgen|divide[12] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.786              -0.786 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.615              -0.615 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.515              -0.515 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.494              -0.494 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.260              -0.260 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.121              -0.121 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.114              -0.114 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.319               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     1.258               0.000 tim:clkgen|divide[12] 
Info (332146): Worst-case minimum pulse width slack is -2.174
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.174           -4392.192 tim:clkgen|divide[12] 
    Info (332119):    -1.000            -386.702 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -169.308 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -142.621 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -135.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -134.955 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -128.746 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -126.650 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -124.271 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     2.839               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     9.709               0.000 clock_50 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.174           -4392.192 tim:clkgen|divide[12] 
    Info (332119):    -1.000            -386.702 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -169.308 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -142.621 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -135.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -134.955 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -128.746 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -126.650 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -124.271 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     2.839               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     9.709               0.000 clock_50 
Info: Analyzing Fast 1200mV 0C Model
Info (332097): The following timing edges are non-unate.  TimeQuest will  assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~4  from: datab  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~0  from: datab  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~3  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~0  from: dataa  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[0].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[1].cog_|cog_ctra|Mux6~4  from: datab  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[2].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~0  from: datab  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~1  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~3  from: datad  to: combout
    Info (332098): Cell: core|coggen[3].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[4].cog_|cog_ctra|Mux6~4  from: datad  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[5].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~0  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[6].cog_|cog_ctra|Mux6~4  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~0  from: dataa  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~1  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~3  from: datac  to: combout
    Info (332098): Cell: core|coggen[7].cog_|cog_ctra|Mux6~4  from: datac  to: combout
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report  Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    Info (11105): For recommendations on closing timing, run Report  Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.545
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -4.545          -11614.439 tim:clkgen|divide[12] 
    Info (332119):    -2.802           -1237.373 pll|auto_generated|pll1|clk[0] 
    Info (332119):    -1.468            -136.289 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.237             -98.156 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.200             -99.567 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.146             -96.658 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.123            -100.517 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.073             -93.888 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.021             -90.654 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.994             -87.034 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -4.545          -11614.439 tim:clkgen|divide[12] 
    Info (332119):    -2.802           -1237.373 pll|auto_generated|pll1|clk[0] 
    Info (332119):    -1.468            -136.289 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.237             -98.156 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.200             -99.567 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.146             -96.658 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.123            -100.517 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.073             -93.888 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.021             -90.654 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.994             -87.034 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
Info (332146): Worst-case hold slack is -0.577
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.577              -0.577 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.576              -2.171 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.570              -2.428 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.409              -0.648 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.251             -16.586 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.237             -17.581 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.039               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.149               0.000 tim:clkgen|divide[12] 
    Info (332119):     0.186               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.196               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.577              -0.577 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.576              -2.171 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.570              -2.428 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.409              -0.648 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.251             -16.586 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.237             -17.581 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.039               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.149               0.000 tim:clkgen|divide[12] 
    Info (332119):     0.186               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.196               0.000 pll|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is -1.428
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.428            -511.565 tim:clkgen|divide[12] 
    Info (332119):    -0.217              -0.217 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.011               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.197               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.274               0.000 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.304               0.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.456               0.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.530               0.000 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.573               0.000 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.428            -511.565 tim:clkgen|divide[12] 
    Info (332119):    -0.217              -0.217 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.011               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.197               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.274               0.000 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.304               0.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.456               0.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.530               0.000 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.573               0.000 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
Info (332146): Worst-case removal slack is -0.295
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.295              -0.295 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.194              -0.194 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.138              -0.138 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.106              -0.106 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.014               0.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.118               0.000 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.176               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.404               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.775               0.000 tim:clkgen|divide[12] 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.295              -0.295 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.194              -0.194 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.138              -0.138 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -0.106              -0.106 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.014               0.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.118               0.000 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.176               0.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.404               0.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     0.775               0.000 tim:clkgen|divide[12] 
Info (332146): Worst-case minimum pulse width slack is -1.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.000           -4148.000 tim:clkgen|divide[12] 
    Info (332119):    -1.000            -207.488 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -118.901 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -113.583 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     2.722               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     9.416               0.000 clock_50 
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.000           -4148.000 tim:clkgen|divide[12] 
    Info (332119):    -1.000            -207.488 dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -118.901 dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -113.583 dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):    -1.000            -112.000 dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|ctr[23] 
    Info (332119):     2.722               0.000 pll|auto_generated|pll1|clk[0] 
    Info (332119):     9.416               0.000 clock_50 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 700 megabytes
    Info: Processing ended: Sun Aug 10 20:07:55 2014
    Info: Elapsed time: 00:00:37
    Info: Total CPU time (on all processors): 00:00:34
    Info: Peak virtual memory: 700 megabytes
    Info: Processing ended: Sun Aug 10 20:07:55 2014
    Info: Elapsed time: 00:00:37
    Info: Total CPU time (on all processors): 00:00:34
Info (293000): Quartus II Full Compilation was successful. 0 errors, 44 warnings

Compilation took 10 mins on an i3-3217U 1.8GHz laptop :frown:

BTW Quartus is able to replace the tabs with spaces.

Ale · 2014-08-11 03:43

I know it doesn't fit. I just wanted to know for how much ;-).
It most probably removed a buch of logic, because I only see 16 RAM blocks being allocated... work in progress. Till that point, it was really fast complaining

Design Information

Command line:   map -a MachXO2 -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial
     PX8A32_XO2_PX8A32_XO2.ngd -o PX8A32_XO2_PX8A32_XO2_map.ncd -pr
     PX8A32_XO2_PX8A32_XO2.prf -mp PX8A32_XO2_PX8A32_XO2.mrp
     C:/02_Elektronik/043_P8X32A/Lattice/PX8A32_XO2.lpf -c 0 -gui
Target Vendor:  LATTICE
Target Device:  LCMXO2-7000HETQFP144
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.1.0.96
Mapped on:  08/11/14  12:39:41


Design Summary
   Number of registers:   4935 out of  7209 (68%)
      PFU registers:         4927 out of  6864 (72%)
      PIO registers:            8 out of   345 (2%)
   Number of SLICEs:      7209 out of  3432 (210%)
      SLICEs as Logic/ROM:   7209 out of  3432 (210%)
      SLICEs as RAM:            0 out of  2574 (0%)
      SLICEs as Carry:        969 out of  3432 (28%)
   Number of LUT4s:        14385 out of  6864 (210%)
      Number of logic LUTs:      12447
      Number of distributed RAM:   0 (0 LUT4s)
      Number of ripple logic:    969 (1938 LUT4s)
      Number of shift registers:   0
   Number of PIO sites used: 115 + 4(JTAG) out of 115 (103%)
   Number of block RAMs:  16 out of 26 (62%)
   Number of GSRs:  1 out of 1 (100%)

jmg · 2014-08-11 15:39

Ale wrote: »

I know it doesn't fit. I just wanted to know for how much ;-).

Interesting, was that for 8 COGs and Full ROM ?
( At least it still reports figures, some tools I've used just report 'failed to fit; when they overflow.. real annoying.)

If those numbers are for 8 COGS, then maybe fewer COGS and less RAM can give a fit.
Others are looking at removing most of the ROM, and doing a loader-time RAM based ROM.

I could see applications where a CPLD is used with a real P1, (or P2) which means even 1-2-3 COGs would be OK in a small companion Logic device.

Ale · 2014-08-12 06:48

Yeah, I used 8 cogs. I should probably go for only 2 or 3, more do not fit

, and it only has 26 kbytes RAM... block RAM

. But, it is sort of what I also achieved with my design...

What is the most suitable FPGA type... Cyclone V, Cyclone IV, Spartan 6, Spartan 3A ?

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