RISC-V, an Open Standard for SoCs

David Betz

This an interesting ISA that might combine well with the P1 to serve as an "app processor" on a chip that uses the P1 for "smart peripherals". Unfortunately, I'm not sure there is an open source implementation of this architecture.

http://www.eetimes.com/author.asp?section_id=36&doc_id=1323406

potatohead

http://www.eecs.berkeley.edu/~waterman/papers/ms-thesis.pdf

That paper is linked in the article above. Very good read.

This ISA is a lot like MIPS. And frankly, MIPS was awesome! SGI optimized the living Smile out of MIPS. Back then I had GCC and MipsPRO on SGI R5K, R10K and 12K chips to tinker with. A build of Xmame, which would take about a day on an Indy R5K done with GCC and MipsPRO was notably different in size and performance.

Would be very interesting to do the same with GCC as it exists today. Probably a lot closer now that the SGI kernel patches got into Linux, and most of that work moved off IRIX and onto Linux, with GCC.

(which just one little reason contributing to why GCC has such good optimization today, IMHO)

Anyway, MIPS with a well sized and smart cache performed like no other! A 300Mhz R10K could compete nicely with a Pentium III running at 1Ghz, and on power consumption? No contest.

This ISA has a lot of the same goodness to it, and I suspect the authors claim of being efficient, compressible, fast, are valid. I like the idea of building on something like RISC-V very much. Hope this idea sees traction.

If we got a nice development board with this ISA implemented reasonably, with Propellers on it, or a general purpose bus of some sort for that purpose, I would think it could be a great environment. Get a nice Linux, clean it up and optimize it, put good tools on there, and the whole thing could be a nice place to work.

That said, I still really like the idea of a no-OS type environment like we are likely to see when we get P2. For development, that has very mixed merits. Won't be for everyone, and we all know that. Just like Linux isn't for everyone either.

But, from an embedded application standpoint, the no-OS, yet capable of doing many things at once in a robust way, promise remains very compelling to me personally.

Leon

We used SGI systems where I once worked. A friend of mine who used to work there as well bought a second-hand Indy a couple of years ago.

The Microchip PIC32 uses a MIPS core.

potatohead

If we would have had open tools sooner, I would very likely have kept an O2 and Indy for development. IRIX is a very sweet environment.

JRetSapDoog

For what it's worth, EET India Daily is reporting:

Headline: India to design first 64bit RISC-V processor

Link: http://www.eetindia.co.in/ART_8800719317_1800001_NT_493813d7_2.HTM

[The second page of the article has more info. with diagrams]

jmg

I had read that, and they are a LONG way from shipping silicon.

In fact, it underlines just how much work is needed, with large teams working for years before they feel ready to tapeout - and that, on what is supposed to be a proven open core ?

Heater.

Meanwhile over in Cambridge the LowRISC guys are hoping to bring RiscV to silicon soon. http://www.lowrisc.org/about/

Their plan is to put multiple little "minion" processors around the RiscV core to handle the real-time peripheral processing.

I don't know about "proven". A year a go they were still writing a large chunk of the spec required for real implementations. Still there are already implementations in real silicon, including made by Samsung: https://en.wikipedia.org/wiki/OpenRISC#Commercial_implementations

KeithE

@Heater - OpenRISC is a different effort. Along those lines I know that hundreds of millions of chips are using BA-22 cores in the field.

Heater.

Ah, sorry, yes. OpenRISC is not RISC V. Got in a muddle there.

Easily done. One or more of the RISC V designers at University of California created what became OpenRISC.

Sorry I don't have a link to that tidbit, I think it came out during one of the videos of the first RISC V conference a year ago.