BE Micro CV is on its way!

Rsadeika

I guess I have a few questions, my desktop is Kubuntu 14.04 64-bit and I have a Windows 7 laptop. I would like to have my BE Micro stuff on the desktop, do they have Quartus in a Linux version? Would it be easier, for a new person, like me, to do this on a Linux setup or a Windows 7 setup?

Ray

David Betz

Rsadeika wrote: »

I guess I have a few questions, my desktop is Kubuntu 14.04 64-bit and I have a Windows 7 laptop. I would like to have my BE Micro stuff on the desktop, do they have Quartus in a Linux version? Would it be easier, for a new person, like me, to do this on a Linux setup or a Windows 7 setup?

Ray

Yes there is a Linux version of Quartus. I have it installed in a VM under VirtualBox on my Mac. It works fine. I was able to build the P1 sources and download my DE0-Nano board.

Rsadeika

So the fun begins. I decided to try the Linux version of Quartus II, the big problem, on my setup which is Kubuntu 14.04 64-bit, is it looks like it insialled the software, but I do not see any way of restarting it once I close the Quartus window. As the final selection in the install process, I chose that an icon be created on the desktop and start the program. No icon on the desktop and no indication as to what folder to look in to start the program. OK after double checking some things, the program start up icon got put into a folder that is labelled 'Desktop', and not actual desktop, as I thought it should be. I guess Kubuntu has to many "Desktops" too deal with.

For the, just starting out, like myself, that will be trying this, the download of Quartus will take close 45 minutes, and the actual install will probably take another 15 minutes, maybe. Next todo will be too read up on some of the items that will be necessary to actually load the Propeller stuff onto the BE Micro CV board and actually see if in fact it really is doing what an actual Propeller chip does.

The next question is, will PropellerIDE or SimpleIDE work with this setup? Then I guess after people start to make adjustments to the FPGA Propeller, who will make adjustments to Spin and/or PropGCC to run the new images?

Ray

David Betz

Rsadeika wrote: »

Then I guess after people start to make adjustments to the FPGA Propeller, who will make adjustments to Spin and/or PropGCC to run the new images?

Ray

I will make changes to PropGCC for simpler changes. I'm afraid adding hubexec may require fairly extensive modifications of the GCC code generator. I'm not sure it will be worth making those changes unless there is some likelyhood of the revised P1 code being fabricated into a real chip.

Rsadeika

I will make changes to PropGCC for simpler changes.

I assume you mean accessing more HUB ram type of changes? It would be interesting to see how Spin would handle a new P1 image with lets say 256K of HUB ram. It seems like with Spin you would have an easier time of dealing with starting of a new COG that could use up to 32K or more of HUB ram.

Ray

David Betz

Rsadeika wrote: »

I assume you mean accessing more HUB ram type of changes? It would be interesting to see how Spin would handle a new P1 image with lets say 256K of HUB ram. It seems like with Spin you would have an easier time of dealing with starting of a new COG that could use up to 32K or more of HUB ram.

Ray

More hub memory, a MUL instruction, stuff like that. I don't think I'll have time to write a completely new code generator.

jazzed

Rsadeika wrote: »

I assume you mean accessing more HUB ram type of changes? It would be interesting to see how Spin would handle a new P1 image with lets say 256K of HUB ram. It seems like with Spin you would have an easier time of dealing with starting of a new COG that could use up to 32K or more of HUB ram.

Ray

Spin can not access more than 64KB of HUB RAM today. Other languages can.

jmg

David Betz wrote: »

More hub memory, a MUL instruction, stuff like that. I don't think I'll have time to write a completely new code generator.

Those would be fine, it will take quite a while for any other more complex variants to pool into some common form.
Better to leave resource for a P2 code generator.

Be interesting to see how much of a P2 can fit into a BEMicro CV - ie how many COGs & SmartPin cells

pjv

Hi All;

I was lucky to get into Arrow just in time to order 2 BE MICROs at $48 each.

Now I'm obligated to, at least try, and learn a whole bunch of new stuff.

If I'm successful in implementing the modifications I need, then my goal is to actually have those chips fabbed, provided the price is not too outlandish.

Hopfully Parallax will see fit to sell them through their network as I'll have no appetite for that.

Wish me luck !

Cheers,

Peter (pjv)

David Betz

pjv wrote: »

Hi All;

I was lucky to get into Arrow just in time to order 2 BE MICROs at $48 each.

Now I'm obligated to, at least try, and learn a whole bunch of new stuff.

If I'm successful in implementing the modifications I need, then my goal is to actually have those chips fabbed, provided the price is not too outlandish.

Hopfully Parallax will see fit to sell them through their network as I'll have no appetite for that.

Wish me luck !

Cheers,

Peter (pjv)

If you're actually going to fab chips I'd like to request that you change the code in the ROM to boot from SPI flash instead of EEPROM.

pjv

David;

It's all a big blur to me just now, but I'm sure that I will be soliciting the forum for ideas in certain directions compatible with my needs, and there will be opportunity to have ad-hoc suggestions considered.

The timing of all this stretches out a loooooong way for me though, so don't expect any results soon.

Cheers,

Peter (pjv)

Cluso99

Sounds interesting Peter. Be sure to keep us updated with your progress.

Heater.

pjv,

...provided the price is not too outlandish...

What is too outlandish for you?

I have no idea about these things but the last time I heard someone talk about it, who had actually done it, they said that today you could probably get a bucket of chips made in some old process for a couple of hundred thousand dollars.

Then of course if you can't sell them because potential customers think that $30 dollars a chip is more outlandish than say $1 then it's all a bit of a waste of money.

Oh yeah, the guy was Andreas Olofsson of Parallella fame. He talks about the cost of getting chips made here: http://www.youtube.com/watch?v=DX9OMgmedbQ and other interesting stuff.

Rsadeika

This should be an interesting forum to watch. Basically there are three board types that will be used by forum members, most are the same members that were/are involved in the shaping of the P2. The direction of the P2 was ultimately controlled by Chip, with the new adaptive P1, each indivdual will have control of a direction. Will be interesting to see where this will all end up? Hopefully some of the adaptive code will be in maybe a modular form, so it could easily be added to your particular board and have it work or will the adaptive code be a specifc FPGA image type and will only work for a particular board? Hopefully something productive will come out of this. LOL Just some ramdom thoughts.

Ray

pik33

This will end up as P3

Rsadeika

This will end up as P3.

Well in that case, why not a hybrid? A lot of geeks here want a more powerfull Propeller, and a lot of folks want something with the power of an ARM, so make a hybrid, and satisfy everybody. So it has a cooling fan, just call it a microprocessor and be done with it. What the heck did I just say...

Ray

David Betz

Rsadeika wrote: »

Well in that case, why not a hybrid? A lot of geeks here want a more powerfull Propeller, and a lot of folks want something with the power of an ARM, so make a hybrid, and satisfy everybody. So it has a cooling fan, just call it a microprocessor and be done with it. What the heck did I just say...

Ray

The ARM would not be what makes it need a cooling fan. ARM processors are probably more power efficient than P1. In any case, you probably can't use the ARM because of licensing issues. Maybe try the OpenRisc core?

Rsadeika

I decided to spend a little time looking at some of this verilog stuff. In the DE0NANOprop1 folder, I found the P8X32A_DE0_Nano folder, and in that folder there are a bunch files, the .v I assume are the verelog files? Since there are 8 .v files which one gets loaded first at compile time by Quartus, in other words which file should I be looking at first, if I want to see or follow the logic? There must be some kind of order and logic involved in this, or maybe it is only supposed to make sense to the author.

I wonder if there is going to be instructions included for the loading up of the Be Micro CV board? If there is such a package, I did not find it.

Ray

potatohead

If people want a micro-processor, then it seems to me making the HUB external is the way to get that done. A Propeller CPU has however many COGS it has, and they look a lot like COGS do today. COG PASM becomes micro-code, in this model.

Take a little tiny chunk of the address space, and have that be the boot code. If there is no RAM connected to the CPU, it runs COG PASM only. Good for boot-strapping / debug / sanity check and nothing else.

HUB RAM is external RAM. Use the egg beater scheme for high throughput, and now it's a multi-core CPU.

mindrobots

Rsadeika wrote: »

I decided to spend a little time looking at some of this verilog stuff. In the DE0NANOprop1 folder, I found the P8X32A_DE0_Nano folder, and in that folder there are a bunch files, the .v I assume are the verelog files? Since there are 8 .v files which one gets loaded first at compile time by Quartus, in other words which file should I be looking at first, if I want to see or follow the logic? There must be some kind of order and logic involved in this, or maybe it is only supposed to make sense to the author.

I wonder if there is going to be instructions included for the loading up of the Be Micro CV board? If there is such a package, I did not find it.

Ray

Ray,

With the changes (.zip file) and instructions Chip provided for the BE Micro, the load went smoothly. If you want, I can post my BE_Micro .xip file with a working .jic in it. Then the instruction would be pretty much the same as loading the Nano with the provided .jic file provided in the original PDF on the Nano product page. (I need to rebuild it with the reset patch and test load it first)

As for the .v files, I haven't really started looking at the source yet. Verilog is different in that it is extremely parallel so it won't be like looking a a normal procedural program where you find main/start/whatever and start from there. I don't want to say any more until I study Verilog more. I don't want to mislead you with any misconceptions I may have.

Maybe someone out there with Verilog experience has some tips for how to scan a new set of files and start constructing in your mind the logic they represent.

jazzed

potatohead wrote: »

If people want a micro-processor, then it seems to me making the HUB external is the way to get that done. A Propeller CPU has however many COGS it has, and they look a lot like COGS do today. COG PASM becomes micro-code, in this model.

Take a little tiny chunk of the address space, and have that be the boot code. If there is no RAM connected to the CPU, it runs COG PASM only. Good for boot-strapping / debug / sanity check and nothing else.

HUB RAM is external RAM. Use the egg beater scheme for high throughput, and now it's a multi-core CPU.

This idea has lots of merit!

Move the bootloader stuff out of usable memory space like pik33 mentioned. Lots of other things need to be considered, but a DE0-Nano with an add-on SRAM module would cost far less than a DE2-115 board. Time for a DE0 memory shield :-)

pik33

DE0-nano has 32 MB SDRAM. There should be a driver for it available (I found some working SDRAM driver for DE2-115). So maybe better use this without adding external SRAM.

mindrobots

I'm still trying to wrap my head around this strange new world.

So if we can take the idea of the block that pik33 created and split it apart into a HUB block, COG blocks and I/O block(s) (maybe a MUX block of some type to glue them together?) then we could effectively swap the standard parts out for custom parts? A new HUB block using SRAM could be built and then COGs hooked to it as long as the COGs could support addressing the new memory. COGs without video could be created to have a smaller COG footprint and you could swap those in and out.

In verilog, is this best done at the block component level? It sounds like the way to go at least for the DE2 to make use of some of the fun stuff on that board. Shields, as Steve mentioned, could work for the Nano as long as there was a Verilog block to support the shield function.

jazzed

pik33 wrote: »

DE0-nano has 32 MB SDRAM. There should be a driver for it available (I found some working SDRAM driver for DE2-115). So maybe better use this without adding external SRAM.

I realize the SDRAM can be used, but doesn't that complicate things horribly? At least with an FPGA driver module all the signalling can be hidden, but it seems like some kind of caching and arbitration thing would be required. Guess it's better than producing a PCB ;-)

Rsadeika

1.1
Overview
This Verilog-A Hardware Description Language (HDL) language reference manual
defines a behavioral language for analog systems. Verilog-A HDL is derived from the
IEEE 1364 Verilog HDL specification. This document is intended to cover the definition
and semantics of Verilog-A HDL as proposed by Open Verilog International (OVI).
The intent of Verilog-A HDL is to let designers of analog systems and integrated circuits
create and use modules that encapsulate high-level behavioral descriptions as well as
structural descriptions of systems and components. The behavior of each module can be
described mathematically in terms of its terminals and external parameters applied to the
module. The structure of each component can be described in terms of interconnected
sub-components. These descriptions can be used in many disciplines such as electrical,
mechanical, fluid dynamics, and thermodynamics.
Verilog-A HDL is defined to be applicable to both electrical and non-electrical systems
description. It supports conservative and signal-flow descriptions by using the
terminology for these descriptions using the concepts of nodes, branches, and ports. The
solution of analog behaviors which obey the laws of conservation fall within the
generalized form of Kirchhoff’s Potential and Flow laws (KPL and KFL). Both of these
are defined in terms of the quantities associated with the analog behaviors.

I found a tutorial for verilog and the above is what I read first, so, I am not sure if had my head screwed on backwards before or it is now srewed on backwards. I thought verilog and all of this was going to be maybe changing a function around, or maybe adding a function, something like the way C works. This is more like, if I understand this correctly, manipulating an analog module to get a desired anolog behaviour which defines your software responses. I think I just might be too old for this kind of cerebral activity, or it will take the rest of my life to figure this out.

I just quickly glanced through the tutorial, now I will have to find a stiff backed chair and try this again at a very slow pace, maybe I will not fall asleep to quickly, this is some strange stuff.

Maybe somebody that knows this stuff already, should strip out seven COGS and then I might have better chance at figuring out analog behaviour of just one COG.

Ray

mindrobots

Rsadeika wrote: »

I found a tutorial for verilog and the above is what I read first,

Try a different tutorial....that writer should be shot...or forced to read their own words.

I think I just might be too old for this kind of cerebral activity, or it will take the rest of my life to figure this out.

Never too old and think what an exciting, rich and fulfilling life it will be!!!
[/quote]

I just quickly glanced through the tutorial, now I will have to find a stiff backed chair and try this again at a very slow pace, maybe I will not fall asleep to quickly, this is some strange stuff.

Again, check out other materials....if you read the introduction and you feel like this, walk away. Some people are more concerned about impressing peers than educating people.

Maybe somebody that knows this stuff already, should strip out seven COGS and then I might have better chance at figuring out analog behaviour of just one COG.

There is just one cog.v, that is a cog definition. Somewhere in the verilog, there is a for loop that just creates 8 instances of that one cog. (one of the other threads had an example where the syntax needed to be changed to support a different FPGA vendor.

Fin the picture in the Boston Expo thread that SRLM posted of the Verilog listings.....amazingly, that *IS* an entire Propeller!!

Rsadeika

There is just one cog.v, that is a cog definition. Somewhere in the verilog, there is a for loop that just creates 8 instances of that one cog.

Yes, I saw that. Strangely enough, I am now intrigued by analog behaviour...

Ray

Rsadeika

It looks like I am getting delivery today, but not sure if I will have time to test it out today.

I have a general question, once you get the P1 image loaded into the BeMicroCV, I guess you can plug in a PropPlug and program the thing. Will the programmed BeMicroCV hold the program once the board is turned off, and then on? I am thinking that I may want to use this as a prototype board for my robot project, although I would need to be able to attach an XBee module to realy have it fit into the robot scheme of things.

Ray

Bill Henning

I believe you will have to add an EEPROM. ( to keep the prop hub image)

Leon

If you program the FPGA configuration device, the FPGA will be reloaded each time the board is powered up.

Rsadeika

Since the BeMicroCV has a uSD on board, I wonder if that could be used instead of an EEPROM? I think somebody is doing something with an SD now. I take it that all the other FPGA boards do not have access to an EEPROM, so maybe access to the SD would be a good thing for storing programs to be run at startup.

Ray