Learning Verilog
mindrobots
Posts: 6,506
(There really needs to be a P1 Verilog/FPGA subforum)
Ok, so now what? Soon I'll be able to build and load and play with a Verilog FPGA image of a P1.
Where do we go from here?
Does anyone have any suggestions as to good Verilog books?? (all the authors seem to be very proud of there creations judging by the price - they are all mostly college texts which is a license to steal)
Online sources?
Favorite videos?
Tips? Tricks? Hints?
Please share, there are probably going to be lots of people (hopefully) wanting to learn Verilog and play along.
*Remember, experts, not everyone has been writing verilog or working with complex tool chains for 25 years, so don't just assume it is an easy switch from one tool to another. We might need a little hand holding and patience.
Ok, so now what? Soon I'll be able to build and load and play with a Verilog FPGA image of a P1.
Where do we go from here?
Does anyone have any suggestions as to good Verilog books?? (all the authors seem to be very proud of there creations judging by the price - they are all mostly college texts which is a license to steal)
Online sources?
Favorite videos?
Tips? Tricks? Hints?
Please share, there are probably going to be lots of people (hopefully) wanting to learn Verilog and play along.
*Remember, experts, not everyone has been writing verilog or working with complex tool chains for 25 years, so don't just assume it is an easy switch from one tool to another. We might need a little hand holding and patience.
Comments
I am with you. Absolutely no background, but also very little time. My strategy is to avoid reading as much as possible. We do know a lot about the Propeller. In my mind, the best approach, given my circumstances, is to simply browse the sources,given what I know about the Propeller and see what happens.
It is all right there in front of us. I'm going to just start hacking away... how hard could it be?
Rich
The problem with verilog tutorials is they starts from simulation stuff which contains a lot of not needed and not synthesable things.
Here:
http://www.ece.umd.edu/class/enee359a.S2008/verilog_tutorial.pdf
is tutorial I used to learn it
The best thing to start is to implement simple demo added to DE2-115 ("My first FPGA"). Try to blink some leds
Prop sources uses some advanced things... SystemVerilog compiler was needed to compile this... Nota thing to get started with.
That I want now is add a RS232 and an EEPROM to the DE2-115 Propeller to get a standalone environment in DE2-115. We can then connect a sound chip (it has a serial interface) and video dac to it. We can even try to recreate HIVE
I never bought any Verilog book. I just looked up things on the internet. There's really not that much you need to know about it.
Verilog was originally developed as a hardware simulation language, so much of 'Verilog' has nothing to do with writing synthesizable code - that is, code which can be compiled into digital logic. What you need to know is about 10% of the overall language.
Consider this: All that you are doing is defining logical equations that are inputs to storage elements (like flipflops or RAM) or drive raw output pins. All inputs to these logical equations are either outputs from storage elements or raw pin inputs (only at the top-most block level do signals attach to raw I/O pins). So, almost all the Verilog code you write will be assignment statements, neglecting the interface lists which name the inputs and outputs to the blocks containing the assignment statements. Everything is organized hierarchically, with all signals being passed up and down through block connections.
Getting a handle on the math/logic operators will get you almost all the way to understanding the P8X32A Verilog code that was posted yesterday. Here is a good place to learn the operators:
http://www.asic-world.com/verilog/operators.html
FPGA - Field Programmable Gate Array
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There are various Verilog Users Group's (Just do a search inside the FPGA Group) For Example:
VERILOG Old Timers
Members OnlyThis group is for former employees of the VERILOG company, based in Toulouse, France.
Digital Logic Design and Verilog HDL
Some groups are only open to professionals.
This is the kind of information I was looking for and hoping to collect here.
"It's not hard." - but you forget, you guys are smarter than the average bears!
http://www.nandland.com/verilog/tutorials/tutorial-introduction-to-verilog-for-beginners.html
Don't forget to search YouTube as well:
https://www.youtube.com/watch?v=MqRBmo5_KZ0
[h=1]Verilog Lecture 1 of 10 - 2009 [/h]
https://www.youtube.com/watch?v=PybxgAroozA
So true. When I saw Ken's announcement, my mind somehow recalled images of the Wizard of Oz. The only difference is that here, the wizards are all real.
And they are so damned charming... makes you want to just dig in and give it a try:)
Rich
http://www.verilog.com/v-books.html
Free Verilog Books (including Introduction to Verilog & Quick Reference Guide):
http://www.freebookcentre.net/Electronics/Verilog-Books-Download.html
You know the old Blaise Pascal quote "I would have written a shorter letter but I didn't have the time." Well, these authors found the time.
As a beginner that does not know what is what you can read whole books and tutorials about the language without anyone ever bothering to tell you you are wasting your time if you just want to blow an FPGA or whatever real logic.
Not only that but you can create a whole pile of VHDL that runs fine under a compiler/simulator like GHDL but is totally useless for your target.
The Verilog Golden Reference Guide by Doulos.
Maybe search the internet.
So far, I find it much easier to read than C and I am neither a C nor Verilog programmer.
"less is more"
That looks good. One other big help is an operator-precedence list, which can be quickly found via Google.
Thanks
User Name has said it all. Small (197 pages) and to-the-point (only synthetizable verilog). I had access to more than a dozen books of Verilog. This one is a keeper. Haven't heard before that quote ... cannot be more appropiate. (It reminds me the book of Kernighan and Ritchie too).
This is fluent. Some not synthesable constructs are synthesable now.
For example in Quartus 12 (maybe 11) and newer you can use initial statement and it is synthesable. Very convenient thing, you can set state of your circuit when it starts.
You can read a few pages here:
http://www0.egr.uh.edu/courses/ece/ECE5440/ece5440_topic2_VerilogIntroduction.pdf
Wouldn't using an 'initial' statement imply the existence of a reset signal? I could see how obvious 'initial' would be in a simulation, but in silicon it would necessitate a reset signal coming from somewhere, since things don't power up in known states, reliably.
Seems to me, that is a path for buggy chips.
An explicit definition will take more effort, but will also be more known too, good or bad.
I don't know how it works internally. They say it is synthesable from quartus (11,12 ? don't remember now). I checked this experimentally. If you state
you will have 1 on port[1] after fpga starts. Now we have reliable "1" after the FPGA start. It is convenient
http://www.ieeeboston.org/edu/on-line_crs/verilog_101_foundations.html