Can P2 pins be shared as regular I/O without just OR'ing? (Chip)
Peter Jakacki
Posts: 10,193
The problem:
I know it has been necessary in the past to allocate a cog for a driver function such as SD cards or even just for a keyboard. However, in Tachyon Forth I have a few helper modules that just get loaded into the same cog that runs the application so it's not necessary to have whole cogs devoted to these driver functions. This does create a problem though in that if I have more than one Tachyon cog wanting to access say the SD card directly, then it can't because the I/O pins have been left high by another cog and there is no way to gain control (The use of pull-up/down resistors could help in some instances). Of course the old Spin method of setting up a new cog would overcome that but then there is no longer any straightforward direct access which turns out to be much simpler in implementing drivers I have found as most of the code is in high-level and also it doesn't need to pass "commands" to drivers and wait, rather, just do it.
So this brings me to the question that I have asked before but I'm sure it's been buried in the all the other frenzied P2 posts in the past, but I'm starting a new thread just to be sure
The question is this: Is it possible for P2 to have I/O pins that can be shared by cogs in a flexible manner? The OR'ing method is almost the exact reverse of what's needed for a basic method as most pins tend to be active low such as chip selects and other pins need to idle high such as serial transmit, I2C etc.
I know it has been necessary in the past to allocate a cog for a driver function such as SD cards or even just for a keyboard. However, in Tachyon Forth I have a few helper modules that just get loaded into the same cog that runs the application so it's not necessary to have whole cogs devoted to these driver functions. This does create a problem though in that if I have more than one Tachyon cog wanting to access say the SD card directly, then it can't because the I/O pins have been left high by another cog and there is no way to gain control (The use of pull-up/down resistors could help in some instances). Of course the old Spin method of setting up a new cog would overcome that but then there is no longer any straightforward direct access which turns out to be much simpler in implementing drivers I have found as most of the code is in high-level and also it doesn't need to pass "commands" to drivers and wait, rather, just do it.
So this brings me to the question that I have asked before but I'm sure it's been buried in the all the other frenzied P2 posts in the past, but I'm starting a new thread just to be sure
The question is this: Is it possible for P2 to have I/O pins that can be shared by cogs in a flexible manner? The OR'ing method is almost the exact reverse of what's needed for a basic method as most pins tend to be active low such as chip selects and other pins need to idle high such as serial transmit, I2C etc.
- Could we have a selectable OR"d or negative logic OR scheme (any low in --> low out) ?
- Could each pin have a resource flag also so that other cogs can vie for that pin when it becomes available?
Comments
On a OR'd COG chain, Libraries would have to idle LOW, and set PinInvert if they wanted the pin to Idle hi.
That would be less Logic than allowing Mux-Select of OR (any 1) or AND (any 0) - as that needs double-up of wide-gates.
( but pin flip does need brain-flip to match )
A Pin-located flag would need to be atomic, which could be a challenge, given the pin structures ?
This works with P1, but one must add the pull up. P2 pins with pull up/down will be a blessing ... the ease of use in other pin features is TBD.