May someone explain exactly how will the ADC work?
The P2 pins have the sigma-delta circuitry built-in (I presume the capacitors). Now that the counters are in the pins can we say that the complete ADC function is in the pins or will the bitsream need to be counted into the cog that now doesn't have the counters anymore? Can we say that the pin have an ADC and when configured as that its counter will be used to build this function locally? Could we read from such pin directly the 8..16? bit ADC value?
When the counters finally make it into the "pins" then yep, they'll complete the ADC hardware. They'll produce a rolling number than can be sampled and diff'd with a previous sample to derive the PCM reading, with the sample interval roughly defining the PCM bit depth.
The reading also might have to be offset to make it a two's complement reading, ie: The reference volt level will be at 50% of the PCM full-scale. Full-scale being the number of clocks in the sample interval.
I think I got it right. Again, haven't actually written any code for this on the Prop1.
obviously the counters are in the pin, else you could not have an adc on every pin. But I hope the way the adc works doesn't change. There still is confusion about this type of adc. It is not delta sigma. What we have is a kind of charge balancer. Continuously the charge transfered to the c from the input resistor is compensated by quantized charge amounts from the digital feedback. So we actually integrate charge. Charge difference over a unified amount of time is called "current". By reading the counter at fixed time intervals, "current" is measured and related to the input voltage. A Delta sigma is made the way, that there is a readout at fixed frequency, reading counter difference, you can not have the integral value. And, as these adcs only have the purpose to follow input voltage there are specialized "decimation"-filters incorporated. The purpose is to allow a high data rate at high resolution. A sampling type adc digitizes the inputs value at a certain time and ideally the slope of the signal doesn't influence the result. A SD-Adc averages the input signal and a goal is to limit the average to a small integration time, so coming close to the signal measured by sampling. The main difference is: when digitizing voice, you know that the signal changes continuously, as voice is generated this way. When digitizing e.g. RADAR, you have a pulsed signal and this signal is only valid when the pulse fully established and you try to exactly measure the peak. So these signals are created "digitally" and show a different characteristic. The propeller ADC is different and e.g. perfect to measure the charge transfered to a battery, as this is an information, not depending (in principle) from the charging time.
obviously the counters are in the pin, else you could not have an adc on every pin.
The original idea with the early Prop2 was to use the Cog counters as momentary samplers, cycling between the modulated bit-stream inputs. It wasn't able to simultaneously read (Using all 8 Cogs) more than 16 bit-streams, just like the Prop1.
I suspect the new layout will not only provide more counters but also be better able to make use of them without having to use all Cogs.
But I hope the way the adc works doesn't change. There still is confusion about this type of adc. It is not delta sigma. What we have is a kind of charge balancer. ...
An R-C charge timer may well be considered the earliest sigma-delta design. I've been googling on the subject myself a little lately and one thing is for sure, sigma-delta ADCs come in many configurations.
I think you'll find that what the Prop is doing is a little better than a basic R-C timer though. The comparator toggles at very high frequency, hence the need for excellent supply decoupling. Both the rise and fall times matter. The counter isn't counting the number of system clocks for one toggle of the comparator; it is counting, like an average, the amount of "high" time of the comparator.
The software can sample this "average" rapidly if it so chooses, and get a very detailed frequency response, or go slower, and have the counter inherently filter higher frequencies but at the same time produce higher resolution samples. There is an intrinsic programmable digital filter as per any other modern sigma-delta designs.
An R-C charge timer may well be considered the earliest sigma-delta design.
;-) If I want to know something, I think, don't google ;-) R-C charge time may, but should not be considered, as SD didn't exist that time. OK, just opposite: SD is NOT R-C. Why? in R-C the voltage of the capacitor changes over time, in SD not. So idealy, there is no way to compare both. But in the real world you can not measure the charge of a cap without removing at least one electron, That make both idealistic systems comparable in the end ;-)
For what it's worth, I will point out that, due to feedback from comparator/inverter, the sigma-delta's integrator (capacitor) voltage does get driven into an oscillation. There is a charge-discharge cycle occurring. It's just a lot purer, as in it's continuous and at extreme overclocking, than your average R-C timer circuit.
You are right, but: with an R-C integrator, change of voltage is a must, with the charge balancer not. An ideal comparator could have an undetectable hysteresis, the feedback pulses could be so small, that a voltage change in the C could not be detected but by the comparator. And: sigma delta ADC has a decimation unit, which the prop adc doesn't have. I like this type of adc, as it perfectly fits my needs ;-)
So we both are right ;-) It always depends on the point of view and sometimes simple things are complicated, that means complicated things become simple. So: a resistor is a voltage controlled current source, as the current generated by a resistor is proportional to the voltage applied. If you can guarantee, that the voltage of the balancing cap doesn't change, the voltage applied to the input resistor (- cap voltage) determines the current through the resistor to the cap. On the other digital side, the voltage applied is constant and so charge per time depends on the duty cycle of the compensation pulses. The prop decimation filter allows for reading integrated values at any time, so much more sophisticated decimation can be done as this is the case with the result you get from a predetermined sigma delta adc. The system balancer/Prop forms the dream team ;-)
The Prop's solution is efficient but not better. And the Prop is performing true sigma-delta ADC. The Prop's counter is the same mechanism that is used in dedicated ICs. And software decimation is still decimation.
Now on to what usually makes sigma-delta's so bulky ... There is often much hardware added inline with the basic sigma-delta circuit for achieving multi-ordered 1-bit modulator-filter combo.
The Prop1's solution is only a first-order modulator (internal inverter and external summing+integrator) plus first-order filter (the counter) plus software decimation.
Now, filters is not something I'm very clued up on but what an "order" appears to represent is similar to the maths power series order. Ie: first order is directly proportional (linear), second order is square law (quadratic), third order is cubic, and so on ... it was pointed out to me in another topic, greater orders can also be post applied by software IIR filtering. I don't know how effective that might be.
Any complexity in the decimation circuit is just a formatting convenience and for providing buffered transfers. The new Prop2 (P16), with it's counters being shifted to the Smart Pins may need some buffering assistance also. Which, in turn, implies a need to do the decimation in hardware. We'll see what Chip comes up with when he gets there.
Now on to what usually makes sigma-delta's so bulky ... There is often much hardware added inline with the basic sigma-delta circuit for achieving multi-ordered 1-bit modulator-filter combo.
The Prop1's solution is only a first-order modulator (internal inverter and external summing+integrator) plus first-order filter (the counter) plus software decimation.
Now, filters is not something I'm very clued up on but what an "order" appears to represent is similar to the maths power series order. Ie: first order is directly proportional (linear), second order is square law (quadratic), third order is cubic, and so on ... it was pointed out to me in another topic, greater orders can also be post applied by software IIR filtering. I don't know how effective that might be.
as discussed in an other thread:
higher order filters provide a greatly improved signal to noise ratio.
but then you have to also take into account the delta-sigma base frequency which is often 10 or 20 MHz
and with the Prop2 could be 200MHz.
so 200MHz 1st order might be comparable to 10MHz 2nd order ... ??
I am not deeply enough into this to make this comparison though ... :-( --- yet ;-)
Comments
The P2 pins have the sigma-delta circuitry built-in (I presume the capacitors). Now that the counters are in the pins can we say that the complete ADC function is in the pins or will the bitsream need to be counted into the cog that now doesn't have the counters anymore? Can we say that the pin have an ADC and when configured as that its counter will be used to build this function locally? Could we read from such pin directly the 8..16? bit ADC value?
The reading also might have to be offset to make it a two's complement reading, ie: The reference volt level will be at 50% of the PCM full-scale. Full-scale being the number of clocks in the sample interval.
I think I got it right. Again, haven't actually written any code for this on the Prop1.
The original idea with the early Prop2 was to use the Cog counters as momentary samplers, cycling between the modulated bit-stream inputs. It wasn't able to simultaneously read (Using all 8 Cogs) more than 16 bit-streams, just like the Prop1.
I suspect the new layout will not only provide more counters but also be better able to make use of them without having to use all Cogs.
An R-C charge timer may well be considered the earliest sigma-delta design. I've been googling on the subject myself a little lately and one thing is for sure, sigma-delta ADCs come in many configurations.
I think you'll find that what the Prop is doing is a little better than a basic R-C timer though. The comparator toggles at very high frequency, hence the need for excellent supply decoupling. Both the rise and fall times matter. The counter isn't counting the number of system clocks for one toggle of the comparator; it is counting, like an average, the amount of "high" time of the comparator.
The software can sample this "average" rapidly if it so chooses, and get a very detailed frequency response, or go slower, and have the counter inherently filter higher frequencies but at the same time produce higher resolution samples. There is an intrinsic programmable digital filter as per any other modern sigma-delta designs.
Curse you Heisenberg! ;-)
Now on to what usually makes sigma-delta's so bulky ... There is often much hardware added inline with the basic sigma-delta circuit for achieving multi-ordered 1-bit modulator-filter combo.
The Prop1's solution is only a first-order modulator (internal inverter and external summing+integrator) plus first-order filter (the counter) plus software decimation.
Now, filters is not something I'm very clued up on but what an "order" appears to represent is similar to the maths power series order. Ie: first order is directly proportional (linear), second order is square law (quadratic), third order is cubic, and so on ... it was pointed out to me in another topic, greater orders can also be post applied by software IIR filtering. I don't know how effective that might be.
Any complexity in the decimation circuit is just a formatting convenience and for providing buffered transfers. The new Prop2 (P16), with it's counters being shifted to the Smart Pins may need some buffering assistance also. Which, in turn, implies a need to do the decimation in hardware. We'll see what Chip comes up with when he gets there.
as discussed in an other thread:
higher order filters provide a greatly improved signal to noise ratio.
but then you have to also take into account the delta-sigma base frequency which is often 10 or 20 MHz
and with the Prop2 could be 200MHz.
so 200MHz 1st order might be comparable to 10MHz 2nd order ... ??
I am not deeply enough into this to make this comparison though ... :-( --- yet ;-)