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SOLVED: Houston, we have a problem... The New P2 doesn't fit. — Parallax Forums

SOLVED: Houston, we have a problem... The New P2 doesn't fit.

Cluso99Cluso99 Posts: 18,069
edited 2014-05-20 12:15 in Propeller 2
UPDATE: Problem solved - P2 can use larger die if necessary.

I have done some silicon calculations based on a number of previous die sizes posted by chip.

Hopefully I have missed something big somewhere, because by my calculations it doesn't fit the available silicon space.

38.400 mm2 = die space available inside i/o pin ring
25.100 mm2 = 512KB Hub
13.300 mm2 = die space remaining

0.372 mm2 = 2KB 2-port cog ram
0.372 mm2 = cog logic (chip said same as memory space)
0.186mm2 = 1KB LUT 1-port
0.930mm2 = total cog space
x16 cogs
15.880mm2 = 16 cogs

0.744mm2 = cog space without LUT
x2.5 space required for new hub interface - fromChip a few days ago
1.580mm2
15.880mm2 = 16 cogs
17.730mm2

But we only have 13.300mm2 available, 4.4mm2 short. That is almost 100KB of hub space.

I truly hope I have missed something here.

Comments

  • Cluso99Cluso99 Posts: 18,069
    edited 2014-05-20 04:33
    1.580 shouldbe 1.850mm2.
  • Brian FairchildBrian Fairchild Posts: 549
    edited 2014-05-20 04:52
    Cluso99 wrote: »
    I truly hope I have missed something here.

    Yep, CORDIC and big multiplier.
  • Cluso99Cluso99 Posts: 18,069
    edited 2014-05-20 05:13
    Brian Fairchild wrote: »
    Yep, CORDIC and big multiplier.

    I was meaning more space, not less space :(
    This just makes it worse unless Chip included it as what he has to do in cog logic, because I included that he expected cog logic to grow to match the cog ram space.
  • Dave HeinDave Hein Posts: 6,347
    edited 2014-05-20 05:28
    You must have missed something in your calculations. I don't think Chip would have followed the new approach if it wouldn't fit.
  • Cluso99Cluso99 Posts: 18,069
    edited 2014-05-20 05:40
    Dave Hein wrote: »
    You must have missed something in your calculations. I don't think Chip would have followed the new approach if it wouldn't fit.
    I agree, and I certainly hope so.
  • cgraceycgracey Posts: 14,206
    edited 2014-05-20 09:18
    I don't want to reconstruct the whole size at the moment, but we are not pushing size limits. We are no longer locked into a 7.3 x 7.3mm die, either. We could go bigger, probably up to 9x9mm. I think this chip will come in around 7 x 7mm, though.
  • Cluso99Cluso99 Posts: 18,069
    edited 2014-05-20 10:15
    cgracey wrote: »
    I don't want to reconstruct the whole size at the moment, but we are not pushing size limits. We are no longer locked into a 7.3 x 7.3mm die, either. We could go bigger, probably up to 9x9mm. I think this chip will come in around 7 x 7mm, though.
    Thanks Chip, I am truly relieved :)
    Heart attack avoided.
  • BaggersBaggers Posts: 3,019
    edited 2014-05-20 11:38
    Cluso99 wrote: »
    0.372 mm2 = 2KB 2-port cog ram
    0.372 mm2 = cog logic (chip said same as memory space)
    0.186mm2 = 1KB LUT 1-port

    Surely the 1KB would be 1/4 the size of the 2KB 2-port cog ram?
  • JRetSapDoogJRetSapDoog Posts: 954
    edited 2014-05-20 12:15
    cgracey wrote: »
    We are no longer locked into a 7.3 x 7.3mm die, either. We could go bigger, probably up to 9x9mm. I think this chip will come in around 7 x 7mm, though.

    Hmm...more smart pins or a standard port? Well, guess that could be revisited after some FPGA-based testing. Never satisfied, are they!

    Wonder what changed in terms of package flexibility. Something about outer ring design (I originally wrote "process," but I don't know how that could affect things) or just found an alternative package solution and/or package house at the right price (or are willing to pay more)? Anyway, not important.
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