Might it simplify the logic if the "L" bit were only used in the "Z" position, instead of Z/C/I positions?
The only potential problem I can see is with the COGID instruction - do we need to check the Z flag on COGID???
Please also check the SETQ instruction - should this have an "L" option?
BTW should CALLB #abs and CALLB @rel have Z=1?
--LS 1100000 L0 I CCCC DDDDDDDDD SSSSSSSSS JP D/#,S/@ ; adr
--LS 1100000 L1 I CCCC DDDDDDDDD SSSSSSSSS JNP D/#,S/@ ; adr
--LS 1100001 L0 I CCCC DDDDDDDDD SSSSSSSSS REP D/#,S/# ;
--LS 1100010 L0 I CCCC DDDDDDDDD SSSSSSSSS WRFAST D/#,S/PTRx ; hub
--LS 1100010 L1 I CCCC DDDDDDDDD SSSSSSSSS WRBYTE D/#,S/PTRx ; hub
--LS 1100011 L0 I CCCC DDDDDDDDD SSSSSSSSS WRWORD D/#,S/PTRx ; hub
--LS 1100011 L1 I CCCC DDDDDDDDD SSSSSSSSS WRLONG D/#,S/PTRx ; hub
--LS 1100100 L0 I CCCC DDDDDDDDD SSSSSSSSS RDFAST D/#,S/PTRx ; hub
--LS 1101000 L0 I CCCC DDDDDDDDD SSSSSSSSS QSINCOS D/#,S/# ; 2
--LS 1101000 L1 I CCCC DDDDDDDDD SSSSSSSSS QARCTAN D/#,S/# ; 2
--LS 1101001 L0 I CCCC DDDDDDDDD SSSSSSSSS QROTATE D/#,S/# ; 3
--LS 1101001 L1 I CCCC DDDDDDDDD SSSSSSSSS QMUL D/#,S/# ; 2
--LS 1101010 L0 I CCCC DDDDDDDDD SSSSSSSSS QDIV D/#,S/# ; 3
--LS 1101010 L1 I CCCC DDDDDDDDD SSSSSSSSS QSQRT D/#,S/# ; 2
-CLS 1101011 L0 I CCCC DDDDDDDDD SSSSSSSSS COGINIT D/#,S/# ;wr if !L 2
-CLS 1101011 L1 I CCCC DDDDDDDDD SSSSSSSSS COGINIT D/#,S/# WC ;wr if !L 2
ZCL- 1101111 0C L CCCC DDDDDDDDD 000000000 CLKSET D/# ;wr if C 1
ZCL- 1101111 ZC L CCCC DDDDDDDDD 000000001 COGID D/# WC ;wr if !WC 0/1
ZCL- 1101111 00 L CCCC DDDDDDDDD 000000011 COGSTOP D/# ; 1
ZCL- 1101111 00 L CCCC DDDDDDDDD 000000101 LOCKRET D/# ; 1
ZCL- 1101111 0C L CCCC DDDDDDDDD 000000110 LOCKCLR D/# ; 1
ZCL- 1101111 0C L CCCC DDDDDDDDD 000000111 LOCKSET D/# ; 1
ZCL- 1101111 00 L CCCC DDDDDDDDD 000001110 QLOG D/# ; 1
ZCL- 1101111 00 L CCCC DDDDDDDDD 000001111 QEXP D/# ; 1
ZCL- 1101111 00 L CCCC DDDDDDDDD 000010000 SETQ D/# ;
ZCL- 1101111 00 L CCCC DDDDDDDDD 000011000 WFWORD D/# ;
ZCL- 1101111 00 L CCCC DDDDDDDDD 000011100 WFLONG D/# ;
--LS 1100000 0L I CCCC DDDDDDDDD SSSSSSSSS WAITPAN D/#,S/# ; *
--LS 1100000 1L I CCCC DDDDDDDDD SSSSSSSSS WAITPAE D/#,S/# ; *
--LS 1100001 0L I CCCC DDDDDDDDD SSSSSSSSS WAITPBN D/#,S/# ; *
--LS 1100001 1L I CCCC DDDDDDDDD SSSSSSSSS WAITPBE D/#,S/# ; *
--LS 1100100 0L I CCCC DDDDDDDDD SSSSSSSSS MSGOUTA D/#,S/# ; *
--LS 1100100 1L I CCCC DDDDDDDDD SSSSSSSSS MSGOUTB D/#,S/# ; *
--LS 1100110 0L I CCCC DDDDDDDDD SSSSSSSSS PICKZC D/#,S/# ; * adr
--L- 1101111 00 L CCCC DDDDDDDDD xxxxx0110 PUSH D/# ; *
--L- 1101111 00 L CCCC DDDDDDDDD xxxxx0111 SETVID D/# ; *
--L- 1101111 00 L CCCC DDDDDDDDD xxxxx1000 WAIT D/# ; *
--L- 1101111 00 L CCCC DDDDDDDDD xxxxx1001 WAITPX D/# ; *
--L- 1101111 00 L CCCC DDDDDDDDD xxxxx1010 WAITPR D/# ; *
--L- 1101111 00 L CCCC DDDDDDDDD xxxxx1011 WAITPF D/# ; *
---- 1101111 00 x CCCC xxxxxxxxx xxxxx1100 SETQ D/# ; *
Good observation! Yes, it would be good to standardize the L-bit position. We don't need COGID to affect Z, either. Only C is vital for COGID.
Thanks for pointing this out. I will make this change on Monday morning.
SETQ does need an # option, as it is used to set cog numbers before COGINIT and also input values to the CORDIC solver in the hub.
Chip,
Perhaps it would be better to have the TESTx or CMPx instructions for the first opcodes '0000000' because with those instructions, a NOP instruction could be used with a 23-bit constant/variable too.
0000000_00x_xxxx_xxxxxxxxx_xxxxxxxxx would do nothing (because no WZ or WC effects, and NR type instruction) and x=23-bit constant/variable
This would be in addition to any instruction with cccc=0000 becomes a NOP...
xxxxxxx_xxx_0000_xxxxxxxxx_xxxxxxxxx does nothing, permitting 3 address fields I, D & S for constants/variables.
New Quartus 14 is out - supposedly much faster compiles due to only re-compiling changed regions. Might speed up your FPGA development cycle.
I thought that was an 'older feature' & tools have been doing that for a while ?
Ahh, I see they say 're-architected Rapid Recompile feature' - seems like a re-spin ?
Could be worth trying.
I thought that was an 'older feature' & tools have been doing that for a while ?
Ahh, I see they say 're-architected Rapid Recompile feature' - seems like a re-spin ?
Could be worth trying.
I noticed in the email from Altera that the speed-up feature is only enabled for the subscription edition, not for the web edition.
-Tor
Ouch, would the cynical suggest the re-spin could be to generate more revenue ?
I think Chip has the subscription edition, as their test board used larger FPGAs ?
Since we are using boards with FPGAs that are covered by Quartus Web Edition, I've let our subscription edition lapse.
I looked into standardizing the L bit location in the op-code and remembered that it's the way it is to conserve on other decoding logic, so I didn't make any changes.
I've got the assembler modified now for the new instruction set and today I hope to get the boot ROM working properly, so that I can download from PNut.exe.
Since we are using boards with FPGAs that are covered by Quartus Web Edition, I've let our subscription edition lapse.
It may pay to check with Altera, to see if the Quartus Web Edition really is just as productive as the subscription edition ? ( Cripple-ware is something of a trend these days...)
I've got the assembler modified now for the new instruction set and today I hope to get the boot ROM working properly, so that I can download from PNut.exe.
Nice going.
Its occurred to me it would be nice to port the monitor across to the P1 as well, for inspecting variables and memory the same way we have been able to do with P2. Potatohead's user oriented document is very good and helpful already...
That's because there is no room on your desk, on your shelves, or in your closets. I blame Erco and the Chinese, but ultimately we have to blame Chip for this. If Chip had become a film maker or a concert pianist, Erco wouldn't be here, and we might be discussing the latest music track from Chip's latest film while looking at our miniature reproductions of Terracotta warriors.
It may pay to check with Altera, to see if the Quartus Web Edition really is just as productive as the subscription edition ? ( Cripple-ware is something of a trend these days...)
In this case the FPGA is only for function proofing after all so it's unlikely to matter in terms of the finished product other than the amount of thumb twiddling time.
Comments
My bad, thanks for the correction!
That's correct. There are also several instructions that must be added for pin<->hub I/O.
Good observation! Yes, it would be good to standardize the L-bit position. We don't need COGID to affect Z, either. Only C is vital for COGID.
Thanks for pointing this out. I will make this change on Monday morning.
SETQ does need an # option, as it is used to set cog numbers before COGINIT and also input values to the CORDIC solver in the hub.
I'll look into the CALL matter.
Perhaps it would be better to have the TESTx or CMPx instructions for the first opcodes '0000000' because with those instructions, a NOP instruction could be used with a 23-bit constant/variable too.
0000000_00x_xxxx_xxxxxxxxx_xxxxxxxxx would do nothing (because no WZ or WC effects, and NR type instruction) and x=23-bit constant/variable
This would be in addition to any instruction with cccc=0000 becomes a NOP...
xxxxxxx_xxx_0000_xxxxxxxxx_xxxxxxxxx does nothing, permitting 3 address fields I, D & S for constants/variables.
Great idea!
Chip:
New Quartus 14 is out - supposedly much faster compiles due to only re-compiling changed regions. Might speed up your FPGA development cycle.
http://www.altera.com/products/software/quartus-ii/whats-new/swf-qts-whats-new.html
I thought that was an 'older feature' & tools have been doing that for a while ?
Ahh, I see they say 're-architected Rapid Recompile feature' - seems like a re-spin ?
Could be worth trying.
-Tor
Ouch, would the cynical suggest the re-spin could be to generate more revenue ?
I think Chip has the subscription edition, as their test board used larger FPGAs ?
I looked into standardizing the L bit location in the op-code and remembered that it's the way it is to conserve on other decoding logic, so I didn't make any changes.
I've got the assembler modified now for the new instruction set and today I hope to get the boot ROM working properly, so that I can download from PNut.exe.
fingers crossed... schedule cleared.
Rich
Nice going.
Its occurred to me it would be nice to port the monitor across to the P1 as well, for inspecting variables and memory the same way we have been able to do with P2. Potatohead's user oriented document is very good and helpful already...
Sounds like it may be almost time to open it up
That's because there is no room on your desk, on your shelves, or in your closets. I blame Erco and the Chinese, but ultimately we have to blame Chip for this. If Chip had become a film maker or a concert pianist, Erco wouldn't be here, and we might be discussing the latest music track from Chip's latest film while looking at our miniature reproductions of Terracotta warriors.
Rich
Careful what you say! Chip has a piano!
Yes, anything that helps is worth considering
I totally missed that somehow! Thanks!
And a Happy Birthday too !! 12 months and a couple of weeks...
And a Happy Birthday too !! 12 months and a couple of weeks...
yes - time flies by
It may pay to check with Altera, to see if the Quartus Web Edition really is just as productive as the subscription edition ? ( Cripple-ware is something of a trend these days...)
In this case the FPGA is only for function proofing after all so it's unlikely to matter in terms of the finished product other than the amount of thumb twiddling time.