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New Hub Scheme For Next Chip

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  • Bill HenningBill Henning Posts: 6,445
    edited 2014-06-28 13:04
    Ooops!

    My bad, thanks for the correction!
    pjv wrote: »
    Bill,

    pjv will not take credit for docs... I suspect that belongs to Peter Jakacki.

    Cheers,

    Peter (pjv)
  • cgraceycgracey Posts: 13,873
    edited 2014-06-29 07:34
    Reviewing that instruction list, would it be fair to assume that the incomplete instructions are for hubexec?

    That's correct. There are also several instructions that must be added for pin<->hub I/O.
  • cgraceycgracey Posts: 13,873
    edited 2014-06-29 07:36
    Cluso99 wrote: »
    Chip,

    I have been looking at your new instruction set.

    Might it simplify the logic if the "L" bit were only used in the "Z" position, instead of Z/C/I positions?

    The only potential problem I can see is with the COGID instruction - do we need to check the Z flag on COGID???
    Please also check the SETQ instruction - should this have an "L" option?
    BTW should CALLB #abs and CALLB @rel have Z=1?
    --LS  1100000  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  JP       D/#,S/@    ;            adr    
    --LS  1100000  L1 I  CCCC  DDDDDDDDD  SSSSSSSSS  JNP      D/#,S/@    ;            adr    
    --LS  1100001  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  REP      D/#,S/#    ;                   
    --LS  1100010  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  WRFAST   D/#,S/PTRx ;            hub    
    --LS  1100010  L1 I  CCCC  DDDDDDDDD  SSSSSSSSS  WRBYTE   D/#,S/PTRx ;            hub    
    --LS  1100011  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  WRWORD   D/#,S/PTRx ;            hub    
    --LS  1100011  L1 I  CCCC  DDDDDDDDD  SSSSSSSSS  WRLONG   D/#,S/PTRx ;            hub    
    --LS  1100100  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  RDFAST   D/#,S/PTRx ;            hub    
    --LS  1101000  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  QSINCOS  D/#,S/#    ;            2      
    --LS  1101000  L1 I  CCCC  DDDDDDDDD  SSSSSSSSS  QARCTAN  D/#,S/#    ;            2      
    --LS  1101001  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  QROTATE  D/#,S/#    ;            3      
    --LS  1101001  L1 I  CCCC  DDDDDDDDD  SSSSSSSSS  QMUL     D/#,S/#    ;            2      
    --LS  1101010  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  QDIV     D/#,S/#    ;            3      
    --LS  1101010  L1 I  CCCC  DDDDDDDDD  SSSSSSSSS  QSQRT    D/#,S/#    ;            2      
    -CLS  1101011  L0 I  CCCC  DDDDDDDDD  SSSSSSSSS  COGINIT  D/#,S/#    ;wr if !L    2      
    -CLS  1101011  L1 I  CCCC  DDDDDDDDD  SSSSSSSSS  COGINIT  D/#,S/# WC ;wr if !L    2      
         
    ZCL-  1101111  0C L  CCCC  DDDDDDDDD  000000000  CLKSET   D/#        ;wr if C     1      
    ZCL-  1101111  ZC L  CCCC  DDDDDDDDD  000000001  COGID    D/#     WC ;wr if !WC   0/1    
    ZCL-  1101111  00 L  CCCC  DDDDDDDDD  000000011  COGSTOP  D/#        ;            1      
    ZCL-  1101111  00 L  CCCC  DDDDDDDDD  000000101  LOCKRET  D/#        ;            1      
    ZCL-  1101111  0C L  CCCC  DDDDDDDDD  000000110  LOCKCLR  D/#        ;            1      
    ZCL-  1101111  0C L  CCCC  DDDDDDDDD  000000111  LOCKSET  D/#        ;            1      
    ZCL-  1101111  00 L  CCCC  DDDDDDDDD  000001110  QLOG     D/#        ;            1      
    ZCL-  1101111  00 L  CCCC  DDDDDDDDD  000001111  QEXP     D/#        ;            1      
    ZCL-  1101111  00 L  CCCC  DDDDDDDDD  000010000  SETQ     D/#        ;            
    ZCL-  1101111  00 L  CCCC  DDDDDDDDD  000011000  WFWORD   D/#        ;            
    ZCL-  1101111  00 L  CCCC  DDDDDDDDD  000011100  WFLONG   D/#        ;            
         
    --LS  1100000  0L I  CCCC  DDDDDDDDD  SSSSSSSSS  WAITPAN  D/#,S/#    ;   *                       
    --LS  1100000  1L I  CCCC  DDDDDDDDD  SSSSSSSSS  WAITPAE  D/#,S/#    ;   *                       
    --LS  1100001  0L I  CCCC  DDDDDDDDD  SSSSSSSSS  WAITPBN  D/#,S/#    ;   *                       
    --LS  1100001  1L I  CCCC  DDDDDDDDD  SSSSSSSSS  WAITPBE  D/#,S/#    ;   *                       
    --LS  1100100  0L I  CCCC  DDDDDDDDD  SSSSSSSSS  MSGOUTA  D/#,S/#    ;   *                       
    --LS  1100100  1L I  CCCC  DDDDDDDDD  SSSSSSSSS  MSGOUTB  D/#,S/#    ;   *                       
    --LS  1100110  0L I  CCCC  DDDDDDDDD  SSSSSSSSS  PICKZC   D/#,S/#    ;   *         adr           
         
    --L-  1101111  00 L  CCCC  DDDDDDDDD  xxxxx0110  PUSH     D/#        ;   *                       
    --L-  1101111  00 L  CCCC  DDDDDDDDD  xxxxx0111  SETVID   D/#        ;   *                       
    --L-  1101111  00 L  CCCC  DDDDDDDDD  xxxxx1000  WAIT     D/#        ;   *                       
    --L-  1101111  00 L  CCCC  DDDDDDDDD  xxxxx1001  WAITPX   D/#        ;   *                       
    --L-  1101111  00 L  CCCC  DDDDDDDDD  xxxxx1010  WAITPR   D/#        ;   *                       
    --L-  1101111  00 L  CCCC  DDDDDDDDD  xxxxx1011  WAITPF   D/#        ;   *                       
    ----  1101111  00 x  CCCC  xxxxxxxxx  xxxxx1100  SETQ     D/#        ;   *                       
    


    Good observation! Yes, it would be good to standardize the L-bit position. We don't need COGID to affect Z, either. Only C is vital for COGID.

    Thanks for pointing this out. I will make this change on Monday morning.

    SETQ does need an # option, as it is used to set cog numbers before COGINIT and also input values to the CORDIC solver in the hub.

    I'll look into the CALL matter.
  • Cluso99Cluso99 Posts: 18,063
    edited 2014-06-29 20:44
    Chip,
    Perhaps it would be better to have the TESTx or CMPx instructions for the first opcodes '0000000' because with those instructions, a NOP instruction could be used with a 23-bit constant/variable too.
    0000000_00x_xxxx_xxxxxxxxx_xxxxxxxxx would do nothing (because no WZ or WC effects, and NR type instruction) and x=23-bit constant/variable

    This would be in addition to any instruction with cccc=0000 becomes a NOP...
    xxxxxxx_xxx_0000_xxxxxxxxx_xxxxxxxxx does nothing, permitting 3 address fields I, D & S for constants/variables.
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-06-30 11:15
    Cluso:

    Great idea!

    Chip:

    New Quartus 14 is out - supposedly much faster compiles due to only re-compiling changed regions. Might speed up your FPGA development cycle.

    http://www.altera.com/products/software/quartus-ii/whats-new/swf-qts-whats-new.html
  • jmgjmg Posts: 14,980
    edited 2014-06-30 12:41
    New Quartus 14 is out - supposedly much faster compiles due to only re-compiling changed regions. Might speed up your FPGA development cycle.

    I thought that was an 'older feature' & tools have been doing that for a while ?
    Ahh, I see they say 're-architected Rapid Recompile feature' - seems like a re-spin ?
    Could be worth trying.
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-06-30 13:56
    For all I know it is only a 0.05% speed increase... but if it is significant, it might help Chip.
    jmg wrote: »
    I thought that was an 'older feature' & tools have been doing that for a while ?
    Ahh, I see they say 're-architected Rapid Recompile feature' - seems like a re-spin ?
    Could be worth trying.
  • TorTor Posts: 2,010
    edited 2014-07-01 02:44
    jmg wrote: »
    Ahh, I see they say 're-architected Rapid Recompile feature' - seems like a re-spin ?
    Could be worth trying.
    I noticed in the email from Altera that the speed-up feature is only enabled for the subscription edition, not for the web edition.

    -Tor
  • jmgjmg Posts: 14,980
    edited 2014-07-01 03:58
    Tor wrote: »
    I noticed in the email from Altera that the speed-up feature is only enabled for the subscription edition, not for the web edition.

    -Tor

    Ouch, would the cynical suggest the re-spin could be to generate more revenue ?
    I think Chip has the subscription edition, as their test board used larger FPGAs ?
  • cgraceycgracey Posts: 13,873
    edited 2014-07-01 09:37
    Since we are using boards with FPGAs that are covered by Quartus Web Edition, I've let our subscription edition lapse.

    I looked into standardizing the L bit location in the op-code and remembered that it's the way it is to conserve on other decoding logic, so I didn't make any changes.

    I've got the assembler modified now for the new instruction set and today I hope to get the boot ROM working properly, so that I can download from PNut.exe.
  • rjo__rjo__ Posts: 2,114
    edited 2014-07-01 11:18
    :))))))))))))

    fingers crossed... schedule cleared.

    Rich
  • jmgjmg Posts: 14,980
    edited 2014-07-01 12:54
    cgracey wrote: »
    Since we are using boards with FPGAs that are covered by Quartus Web Edition, I've let our subscription edition lapse.
    It may pay to check with Altera, to see if the Quartus Web Edition really is just as productive as the subscription edition ? ( Cripple-ware is something of a trend these days...)
  • TubularTubular Posts: 4,476
    edited 2014-07-01 20:12
    cgracey wrote: »
    I've got the assembler modified now for the new instruction set and today I hope to get the boot ROM working properly, so that I can download from PNut.exe.

    Nice going.

    Its occurred to me it would be nice to port the monitor across to the P1 as well, for inspecting variables and memory the same way we have been able to do with P2. Potatohead's user oriented document is very good and helpful already...
  • RaymanRayman Posts: 12,924
    edited 2014-07-02 06:29
    My DE2 is still sitting in unopened Parallax box on the floor in my office. I think the box arrived the same day the old P2 died...

    Sounds like it may be almost time to open it up :)
  • rjo__rjo__ Posts: 2,114
    edited 2014-07-02 08:14
    Rayman,

    That's because there is no room on your desk, on your shelves, or in your closets. I blame Erco and the Chinese, but ultimately we have to blame Chip for this. If Chip had become a film maker or a concert pianist, Erco wouldn't be here, and we might be discussing the latest music track from Chip's latest film while looking at our miniature reproductions of Terracotta warriors.





    Rich
  • jazzedjazzed Posts: 11,803
    edited 2014-07-05 12:57
    rjo__ wrote: »
    If Chip had become a film maker or a concert pianist, ....


    Careful what you say! Chip has a piano!
  • ozpropdevozpropdev Posts: 2,786
    edited 2014-07-05 20:05
    Would that then make the new chip the 12th root of P2? :lol:
  • Heater.Heater. Posts: 21,230
    edited 2014-07-06 04:28
    ozpropdev,
    Would that then make the new chip the 12th root of P2?
    I seriously hope not. I hope we are transposing up by a couple of octaves or more from P1.
  • SeairthSeairth Posts: 2,474
    edited 2014-07-07 16:15
    I just noticed that Altera released Quartus 14.0 in June. Any idea if it's worth the upgrade for the current design effort?
  • TubularTubular Posts: 4,476
    edited 2014-07-07 23:22
    Seairth there was a bit of discussion about it already, see post 1086 onwards, just above

    Yes, anything that helps is worth considering
  • SeairthSeairth Posts: 2,474
    edited 2014-07-08 08:19
    Tubular wrote: »
    Seairth there was a bit of discussion about it already, see post 1086 onwards, just above

    Yes, anything that helps is worth considering

    I totally missed that somehow! Thanks!
  • MJBMJB Posts: 1,235
    seems a bit forgotten - so I give it  a bump
  • jmgjmg Posts: 14,980
    seems a bit forgotten - so I give it  a bump


    And a Happy Birthday too !!  12 months and a couple of weeks...
  • MJBMJB Posts: 1,235
    seems a bit forgotten - so I give it  a bump


    And a Happy Birthday too !!  12 months and a couple of weeks...


    yes - time flies by

  • evanhevanh Posts: 13,853
    edited 2015-07-31 06:07

    It may pay to check with Altera, to see if the Quartus Web Edition really is just as productive as the subscription edition ? ( Cripple-ware is something of a trend these days...)


    In this case the FPGA is only for function proofing after all so it's unlikely to matter in terms of the finished product other than the amount of thumb twiddling time.

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