If we were talking about the other video engine, I would potentially agree. It is a serious bit of silicon. What we are likely to get in this design isn't worth trading for. The question is simply whether or not USB and or SERDES make sense to do, and or whether they are per COG, or a HUB feature like the math is likely to be.
Right now Chip is completing the ALU. If he goes like he has in the past, he will establish what a COG is, then build out from there.
The pins were discussed early, and I think the question of what goes in 'em depends a lot on what a COG will look like this time.
The math block he built looks like it's gonna be in the HUB. That suggests to me, he's going to pluck some things from the other design, then maximize this one. USB on pins would still be an open question at this point, IMHO.
1. Poor single thread of execution performance
2. No built-in ADCs
3. Not enough global memory space for expanding applications
4. Not enough pins
5. Software defined peripherals are slower than hardware solutions
6. Requires external support chips for USB, storage, and crystal
7. Relatively expensive
8. Forum contributors always argue ;-)
Comments
I might have missed a memo there.
The pins were discussed early, and I think the question of what goes in 'em depends a lot on what a COG will look like this time.
The math block he built looks like it's gonna be in the HUB. That suggests to me, he's going to pluck some things from the other design, then maximize this one. USB on pins would still be an open question at this point, IMHO.
Code Protection?