SPI chip select expansion
richaj45
Posts: 179
Hello:
I have below a three IC solution to expand SPI chip select lines without using anymore than the five basic SPI pins. Those are Serial Data Out (SDO), Serial Clock (SCLK, Chip Select (CS), and Serial Data In (SDI). The trick is used CS to select from shifting out SDO to a CSx select register or out to the selected SPI peripheral.
The attached schematic show the three parts used, a 74HC378, 74HC138, and a 74HC251.
The '378 is a 6-bit D-type register with and enable. When the enable is low the device loads each register bit on the rising edge of the clock SCLK. When the '378 enable is high any clocks edge have no effect and the data clocked in is held. Since the '378 contains 6 individual flops, they are wired Q out to D in to form a 6-bit shift register.
After the '378 is loaded with a 4-bit select value the CS is taken high which enables the '138 3-to-8 decoder which outputs a single active low chip select that follows the rise and fall of CS.
The chip select bits from the '378 also run to a 8-to-1 mux that will route the selected SPI device output to the SDI input pin of the Prop.
There is a simple timing diagram showing the selection of CS3# and input SDI3.
Note that the 74HC378 is an obsolete 6-bit part that i picked up on ebay. A non-obsolete 8-bit part is the 74HC377.
Also not that the 4-bit of the '378 register is going to an active low enable on the '138 and '251. Therefore by adding a inverter in the 4Q bit and running it to another set of '138, '251 chips another 8 SPI devices can be added with out any more pins, of course.
I have the parts but have not put it together yet or written a driver yet, but i will in time. I thought others might find this useful in the idea state.
Now if i can figure out how to attached a .pdf file ....
cheers,
rich
I have below a three IC solution to expand SPI chip select lines without using anymore than the five basic SPI pins. Those are Serial Data Out (SDO), Serial Clock (SCLK, Chip Select (CS), and Serial Data In (SDI). The trick is used CS to select from shifting out SDO to a CSx select register or out to the selected SPI peripheral.
The attached schematic show the three parts used, a 74HC378, 74HC138, and a 74HC251.
The '378 is a 6-bit D-type register with and enable. When the enable is low the device loads each register bit on the rising edge of the clock SCLK. When the '378 enable is high any clocks edge have no effect and the data clocked in is held. Since the '378 contains 6 individual flops, they are wired Q out to D in to form a 6-bit shift register.
After the '378 is loaded with a 4-bit select value the CS is taken high which enables the '138 3-to-8 decoder which outputs a single active low chip select that follows the rise and fall of CS.
The chip select bits from the '378 also run to a 8-to-1 mux that will route the selected SPI device output to the SDI input pin of the Prop.
There is a simple timing diagram showing the selection of CS3# and input SDI3.
Note that the 74HC378 is an obsolete 6-bit part that i picked up on ebay. A non-obsolete 8-bit part is the 74HC377.
Also not that the 4-bit of the '378 register is going to an active low enable on the '138 and '251. Therefore by adding a inverter in the 4Q bit and running it to another set of '138, '251 chips another 8 SPI devices can be added with out any more pins, of course.
I have the parts but have not put it together yet or written a driver yet, but i will in time. I thought others might find this useful in the idea state.
Now if i can figure out how to attached a .pdf file ....
cheers,
rich
Comments
Just need to remember that the CS is now active high from Prop to give a CS low at the SPI device.
Looking at the date on your schematic just confirms that this solution is ahead of its time
CogSaver