What Chip Said
rjo__
Posts: 2,114
@#1187
Well before that, Chip said that hub exec would operate at 50% of cog bandwidth....link lost:)
I want what everyone else wants, unless (of course) it interferes with what I really want, in which case, I am against it, unless of course it sells a lot of chips, in which case I am for it, unless it slows down development, in which case, I'm against it, unless the net gain is substantial, in which case I am for it.
In my mind, everything you guys are suggesting is just fine, unless it lowers cog speed, in which case, I'm against it, unless (of course)...
Rich
http://forums.parallax.com/showthread.php/155132-The-New-16-Cog-512KB-64-analog-I-O-Propeller-Chip/page60It's looking likely that the main clock could go 250MHz. In that case, 125 MIPS x 16 cogs = 2000 MIPS total.
Well before that, Chip said that hub exec would operate at 50% of cog bandwidth....link lost:)
I want what everyone else wants, unless (of course) it interferes with what I really want, in which case, I am against it, unless of course it sells a lot of chips, in which case I am for it, unless it slows down development, in which case, I'm against it, unless the net gain is substantial, in which case I am for it.
In my mind, everything you guys are suggesting is just fine, unless it lowers cog speed, in which case, I'm against it, unless (of course)...
Rich
Comments
Enjoy!
Mike
Rich,
I think you are saying "You were against it, before you were for it", but now it sounds like "You were for it, before your were against it" - So now I am lost and really confused also :-)
I have one URL (link) that keeps me sane and up-to-date (with NO frills or long discussions), the link is:
forums.parallax.com/search.php?do=finduser&userid=41126&contenttype=vBForum_Post&showposts=1
It links to Chip's posts, I use it as a Bookmark, for my habitual hourly Quick-Prop-Fix.
Note, you can NOT save the results of the above URL as a Bookmark, it is a one-time search. But, you can save the above URL as a Bookmark.
--
You're likely thinking of a statement nested within Chip's tentative plan for the new chip.
The 3rd line of the CODE section says: "16 cogs with 2-clock instructions, hub execution at 50% cog speed" (emphasis = underlining added)
Tentative Plan: http://forums.parallax.com/showthread.php/155132-The-New-16-Cog-512KB-64-analog-I-O-Propeller-Chip?p=1260747&viewfull=1#post1260747
This is correct. We spoke yesterday and it looks like the latest specs are more like 200 MHz/80 MIPS per cog. He's working on finishing the ALU right now and hopes to have an FPGA image in a couple of weeks. I'm discouraging him from visiting the forums and trying to keep distractions away from his field of view right now.
Ken Gracey
I realize that these aren't fixed numbers, of course. But how does one slice 200 MHz to get 80 MIPS? That would be 2.5 clocks/instruction. Maybe it'll only be 160MHz?
I'm very, very glad to hear this!
So the last week's worth of hand-wringing hasn't distracted Chip, and we may see some form of hubsharing as last discussed then?
The first part of that, at least...
Those are slightly strange combination numbers ?
200MHz was the original (respin) target, but 80MIP COGs suggest 160MHz ceiling - which conflicts with the 200MHz ?
Or 240MHz, but that would mean that instructions would be effectively 3 clock cycles, which feels a little odd.
or, since we are doing odd
I think this is correct - it must've been 160 MHz.
The FPGA version is likely going to run at 160Mhz with 80MIPs for the COGs. The real chip is still going to be 200Mhz with 100MIPs COGs.
Sounds good, and what I had guessed would be anticipated at this stage. (ie ASIC still faster than FPGA)
Roy, tell Chip I said hi.
Good plan, but perhaps you should take some inspiration from the vacuum tube days of TV manufacturing. Rumor had it that the design engineers were locked in a room until they came up with a design that used one less tube than the current year's model ;-)