When I was an undergraduate at Case Institute of Technology, the university computer center had a Univac 1107. They also had an operational Univac I which one of the railroads leased for keeping track of their freight cars. They had their own Univac I which was running all the time and not up to handling their freight volume, so they went to multiprocessing (two Univac Is) for the throughput and redundancy. Talk about legacy maintenance. The Univac I was actually up more than the 1107.
I'm not sure how we got from Arduino and Propellers to UNIVAC 1100's but I'll always talk about those.
The multiprocessing Univac I must have worked so well that they decided multiprocessing was the future. The 1108 followed the 1107 and soon, it had a multiprocessor version. From there on out, you could always get a multiprocessor 1100 in some configuration or another. They were true symmetrical multiprocessors and really fun beasties to work on. The most fun I've ever had and still got paid for it!!
Which brings me back to the Propeller - the multiprocessor capabilities are one of the things that keeps me playing with the Prop and anticipating the new chip. I used to have a customer with a $1M mainframe to have this kind of fun!!
Some samples of cool SPIN + PASM DAT section specification methods:
foobard 'memory fill
byte 2[300]
'some bytes aligned on word boundaries
byte word 5[64],4[64],3[64],2[64]
'some words aligned on long boundaries
word long "ea", 3, $face, %10101[50]
'handy delimiters
long $10_33_10_33, %%0123_01230123
'binary bitfield
long %10_101101_10_1010_10100_0
'two bits per pixel
one_number byte %%0123
'misc
byte "hello", $3, %10101, %%0123
'some mask
long %10110<<7 'shift pattern left 7 bits
long %%230100000000>>4 'shift pattern right
'mix it up some
long $43<<2, %%332211+480, (one_number<<5) & $ff00ff00
Often, I find I can just think in whatever base I want, and express values in simple terms, doing basic booleans and math, etc... which is just handy. Many of the same expressions work to express literals in a program or DAT section. Once a person has learned a few simple things about expressions and how to specify various values, that info works all over the place. It's just nice.
Sorry for the lame example, but it should serve to address the point I made earlier. Not a show stopper, but just a very nice to have.
I looked at the link in the first post, and while there were some responses from the propeller experts, the last post is from June 30 with the OP complaining about the "failure" to release the P2 FPGA image by the "unofficial milestone" of Spring 2015 along with complaints about the lack of info from Parallax.
I would like to recommend that some of the folks working with the FPGA images post a reply to that post giving explaining what's going on with the testing and development and some of the features that are being developed as well as a link to the relevant threads.
Tom, are you suggesting someone post an update over at the Adafruit forum?
Best source of current information is the google doc(s) at the top of the FPGA image thread.
I'm not sure people on other forums understand the nature of the open (but drawn out) development process we're engaged with here. I suspect best thing to do is finish the P2 chip and documentation and everything will be easier.
Definitely not a full update or anything that would give the impression that a series of updates should be expected.
I was thinking just a post stating that the initial FPGA image was released in ?September? 2015, that open testing & ?development/optimization? are proceeding, and possibly mentioning some of the early user software development (e.g. Dave's, Peter's, etc), together to the link to the FPGA image thread. The reason is that the "final" post in the adafruit thread was so negative, and leaving it that way seems to reinforce the negativity.
I'd try, but since my understanding of the process and how and what is being done is so low, I'd screw it up for sure.
Just a suggestion.
On the other hand, if that adafruit thread has essentially died, maybe just let it be.
Given how things have gone, negative is super easy. Outside the group working on it, that is what will happen. People want stuff they can use today, right now. When they get excited, find out that's not the case, out comes the negative.
Right now, people can use an FPGA and do a lot of interesting stuff, but it's testing, etc...
When the real chip gets sent off for the shuttle run, we will have a firm set of specs to consider and the FPGA to learn about.
When we get working chips, then it's time to talk it up, IMHO.
Yeah I understand where you're coming from Tom. However I think that thread is sufficiently buried. There's quite a few out there (and here) that give out-of-date guidance
The OP feels let down because the (somewhat contrived) unofficial deadline passed without Parallax giving regular-enough updates. That's understandable. I vaguely remember that long silence and at the end of it the "plan" turned out to be exactly what parallax said they were intending to do. But rumors and doubt grow during the silence
Comments
I'm not sure how we got from Arduino and Propellers to UNIVAC 1100's but I'll always talk about those.
The multiprocessing Univac I must have worked so well that they decided multiprocessing was the future. The 1108 followed the 1107 and soon, it had a multiprocessor version. From there on out, you could always get a multiprocessor 1100 in some configuration or another. They were true symmetrical multiprocessors and really fun beasties to work on. The most fun I've ever had and still got paid for it!!
Which brings me back to the Propeller - the multiprocessor capabilities are one of the things that keeps me playing with the Prop and anticipating the new chip. I used to have a customer with a $1M mainframe to have this kind of fun!!
UK, too.
Jon, you were supposed to say "your smile," even if you were thinking something else!
I was young and stupid. I'm no longer young.
Some samples of cool SPIN + PASM DAT section specification methods:
foobard 'memory fill byte 2[300] 'some bytes aligned on word boundaries byte word 5[64],4[64],3[64],2[64] 'some words aligned on long boundaries word long "ea", 3, $face, %10101[50] 'handy delimiters long $10_33_10_33, %%0123_01230123 'binary bitfield long %10_101101_10_1010_10100_0 'two bits per pixel one_number byte %%0123 'misc byte "hello", $3, %10101, %%0123 'some mask long %10110<<7 'shift pattern left 7 bits long %%230100000000>>4 'shift pattern right 'mix it up some long $43<<2, %%332211+480, (one_number<<5) & $ff00ff00Often, I find I can just think in whatever base I want, and express values in simple terms, doing basic booleans and math, etc... which is just handy. Many of the same expressions work to express literals in a program or DAT section. Once a person has learned a few simple things about expressions and how to specify various values, that info works all over the place. It's just nice.
Sorry for the lame example, but it should serve to address the point I made earlier. Not a show stopper, but just a very nice to have.
I would like to recommend that some of the folks working with the FPGA images post a reply to that post giving explaining what's going on with the testing and development and some of the features that are being developed as well as a link to the relevant threads.
Tom
Best source of current information is the google doc(s) at the top of the FPGA image thread.
I'm not sure people on other forums understand the nature of the open (but drawn out) development process we're engaged with here. I suspect best thing to do is finish the P2 chip and documentation and everything will be easier.
I was thinking just a post stating that the initial FPGA image was released in ?September? 2015, that open testing & ?development/optimization? are proceeding, and possibly mentioning some of the early user software development (e.g. Dave's, Peter's, etc), together to the link to the FPGA image thread. The reason is that the "final" post in the adafruit thread was so negative, and leaving it that way seems to reinforce the negativity.
I'd try, but since my understanding of the process and how and what is being done is so low, I'd screw it up for sure.
Just a suggestion.
On the other hand, if that adafruit thread has essentially died, maybe just let it be.
Tom
Given how things have gone, negative is super easy. Outside the group working on it, that is what will happen. People want stuff they can use today, right now. When they get excited, find out that's not the case, out comes the negative.
Right now, people can use an FPGA and do a lot of interesting stuff, but it's testing, etc...
When the real chip gets sent off for the shuttle run, we will have a firm set of specs to consider and the FPGA to learn about.
When we get working chips, then it's time to talk it up, IMHO.
Prior to that time, what's the point?
The OP feels let down because the (somewhat contrived) unofficial deadline passed without Parallax giving regular-enough updates. That's understandable. I vaguely remember that long silence and at the end of it the "plan" turned out to be exactly what parallax said they were intending to do. But rumors and doubt grow during the silence