Exposure: WIZnet W5500 Competition 2014 and "P2"
Peter Jakacki
Posts: 10,193
Everyone talks about exposure and I'm betting that if my submission to Circuit Cellar this year for the WIZnet W5500 competition is with a P2 then that will certainly be quite some exposure. But that's just one little thing, there are many more. For this contest I'm looking at home automation and smartphone access so I will probably use and enhance Tachyon Forth for this. Yes, I could do it with a P1 as I have already done but all things Ethernet just like to have lots of memory and speed, something which the P16X32B chip will not be lacking.
Comments
http://www.ti.com/tool/ek-tm4c1294xl?DCMP=PPC_Google_TI&k_clickid=473199e5-a006-82a8-fabe-00005b4f449d#close
I've been playing with one, and it works very well.
Thanks for the link Leon. I'm surprised you haven't been banned from here for promoting alternatives
However the point is not whether it's cheaper, it's the flexibility and sheer real-time deterministic processing power of 16 cores and the whopping 512kB RAM besides all the other specials that will grab much attention, especially when I have it performing tasks which would not be easy to handle with other 32-bit micros, even if they do have an M4 core, it's still only a single core although it's good to see that they have integrated a PHY. Perhaps a lot of these peripheral features that these single cores list should also be listed for the P2 albeit in "configurable core" fashion.
Also not to be underestimated is the support that the forum supplies, there's nothing else like it. Perhaps this should be included in the P2 features.
Maybe, but Circuit Cellar seem to not list your LaunchPad board from TI, on the list of ELIGIBLE PARTS here ?
http://circuitcellar.com/wiznet2014/eligibleparts/
Sounds interesting, and I'd guess a FPGA Eval version is going to be fine ?
Deadline looks to be August 3, 2014 , so that should be just ok ?
If I design a pcb with a dual footprint so that when I submit an entry it might be with the P1 but I can at least highlight P2 in the "P2 option" feature list as it is one and the same pcb. Seeing that the P1 handles this task but you have plenty of room to upgrade to the P2 instead will attract attention.
As for the FPGA version I will use that to test out the new pcb so that I can also publish performance specs for this P2 option. If I somehow manage to get a P2 chip the day before I submit then I can certainly show that I have a version with the P2.
It could make a good demo of Tachyon Forth, as the same code should run on both targets ?
(well all 3 targets eventually, the P1, the FPGA-P2 and the real P2).
I doubt a real P2 will be there in time, but I don't see problems with proving using FPGA boards - even the cheaper BeMicro CV should be able to emulate the next version.
I'm a realist so I don't expect everyone or even anyone to start using Forth but it's the environment that I know I can get the job done in and with. For anyone contemplating doing this in C then P2 will be essential to making that happen. I know August is perhaps too soon even to see a P2 but by the time the contest is judged and published I might be able to have photos up of the P2 board but I certainly don't want to dummy it at all and have that backfire.