I would be more measured.
Wait for final FPGA fit values, as those tend to come down a little, and Power Envelope is still not gone away, so the final die MHz values may come with Power caveats. I've still not seem confirmed counter MHz values either.
One good sign of faster partial-design figures, is they indicate less overall logic and that should translate into power savings.
(even if something else ultimately sets the MHz )
RossH,
Certain people got carried away?! You think anyone other than Chip, Beau, & Ken caused the P2 to not be finished "over a year ago" ? Are you that out of touch with things?
I'm seriously tired of people pointing fingers at forum members and others as the reason the P2 got so many new features added and failed to be a viable chip on the intended process. You're all wrong and completely annoying the heck out of me with all these baseless false accusations. The P2 is what it is because Chip and Beau chose to do it and Ken supported them.
You think anyone other than Chip, Beau, & Ken caused the P2 to not be finished "over a year ago" ? Are you that out of touch with things?
Yes, and no, in that order. This is not a false observation.
For example. One day I happened to read about the P2's support for task switching. I't immediately occurred to me that this could be automated to create efficient hardware time-sliced threads. So I asked if it was a possibility to do that.
Two weeks later hardware scheduled threads were in. I'm sure a bunch more time went into integrating hardware threading with other features, optimizing and so on. Before you know it that's 10% or so of the one year of overrun.
Is that the only such case of the design following forum input? I don't think so.
Of course the act of ripping all that out is more delay.
Chip, is his own man of course. However he can't resist exploring interesting ideas...thank goodness.
Nobody should be blaming anybody. But you must admit there has been a feed-back loop going on between forum folks and Chip for a long time. Else why is all this extensive debate been going on for ages?
I hold myself up as being in a very small part a contributor to that feed back loop. That loop lead to a design that was unworkable. And some would say wasted a year.
I'm very confident that things are on the right track now and that all Chip has learned will be used to good effect.
... That loop lead to a design that was unworkable. And some would say wasted a year.
No, that's far too simplistics. I'd even say wrong. The Prop2 was on target as a beefy design long before that. Had the first shuttle run worked I think you would have seen a hot IC result from even that.
There is no use going down the blame game. What has happened has happened. A lot has been learnt, and will make for a much better targeted chip when its done.
IMHO the hubexec has been the biggest and single most benefit to come out of all this reworking. This was discovered in a fairly innocent discussion last Thanksgiving. It did however, have a big impact on the design, but probably the P2 was over budget on power anyway.
Now, the new P1+/P2, has 512KB of hub (major plus), 16 cogs (simpler and leaner) (major plus), and Chip seems to be able to crank the speed up as a result (another plus, because we lost some speed from the original P2 design).
Some of you may not have realised, but much of the smart I/O was already there, just hidden from us in special instructions.
RossH,
Certain people got carried away?! You think anyone other than Chip, Beau, & Ken caused the P2 to not be finished "over a year ago" ? Are you that out of touch with things?
Since I do believe that, then yes, I guess I am "that out of touch".
I do not resile from any of the comments I have made. We could have had a workable P2 over a year ago. Now, it looks like we might have something that looks a lot like that chip again now. A year late.
No, that's far too simplistics. I'd even say wrong. The Prop2 was on target as a beefy design long before that.
No doubt simplistic, I have not kept up with every detail of debate and progress here and for I sure know very little about getting an actual chip made.
Not totally wrong though. Clearly in all those months of debate, wrangling, and feature accumulation we forgot to check if the thing was actually buildable.
Clearly in all those months of debate, wrangling, and feature accumulation we forgot to check if the thing was actually buildable.
Thermal behaviour had never been check for irrespective of forum involvement. It's just one of the stepping stones is all. Associating this hiccup with the forum is wrong.
I sincerley hope it's only a "hiccup" in in time. But from here it looks like a major rearchitecting. The sort of thing that would give my boss and our backers heart failure.
I look forward to Chip writing a follow on story "Why the Propeller II works" with all the gory details of the trials and tribulations along the way and how the collaborative approach helped and/or hindered progress.
Actually, we could not have had a P2 over a year ago - the shuttle runs failed before the recent changes, so saying that we could have had a P2 over a year ago is factually incorrect.
The P2 has been brewing for something like 8 years now, so the last year and a bit can't take the blame. It has only been what - two or three years - since the switch to verilog.
Chip, Ken and Beau want a really competitive chip. They want this so that money will be made to fund the future. (among other things)
That was done.
Now, the process physics mandate a different approach. A ton was learned about how to design a killer chip in this process.
They still want a really competitive chip. The future, among other things, needs to be funded. Right now, Chip is maximizing what he learned so that the end result is as awesome as possible.
Yes, we have a feedback loop going on, and it's an important one because it helps trigger Chip's thinking in ways he would not have otherwise and that has been determined to be a good thing.
Relax, voice your opinion and let the process that has evolved here happen and we are going to get an awesome chip!
Personally, I agree with Roy. This design is looking great! The emphasis on features changed a little and for the better, again in this process physics.
Nobody should be blaming anyone.
Chip and Ken have mentioned over the years how Chip tends to work alone and when they saw the need for Chip to interact more, get some fuel for the mental fire he really needs to shine bright, they did that. What we say here is important. But it's not something we need blame ourselves for, because the simple truth is what we say here is also necessary.
Comments
I would be more measured.
Wait for final FPGA fit values, as those tend to come down a little, and Power Envelope is still not gone away, so the final die MHz values may come with Power caveats. I've still not seem confirmed counter MHz values either.
One good sign of faster partial-design figures, is they indicate less overall logic and that should translate into power savings.
(even if something else ultimately sets the MHz )
Yes, but it also demonstrates that we could have had the P2 over a year ago if certain people had not got so carried away.
I still have my fingers crossed that this does not occur again, and I'm sure many others do also.
Ross.
Certain people got carried away?! You think anyone other than Chip, Beau, & Ken caused the P2 to not be finished "over a year ago" ? Are you that out of touch with things?
I'm seriously tired of people pointing fingers at forum members and others as the reason the P2 got so many new features added and failed to be a viable chip on the intended process. You're all wrong and completely annoying the heck out of me with all these baseless false accusations. The P2 is what it is because Chip and Beau chose to do it and Ken supported them.
For example. One day I happened to read about the P2's support for task switching. I't immediately occurred to me that this could be automated to create efficient hardware time-sliced threads. So I asked if it was a possibility to do that.
Two weeks later hardware scheduled threads were in. I'm sure a bunch more time went into integrating hardware threading with other features, optimizing and so on. Before you know it that's 10% or so of the one year of overrun.
Is that the only such case of the design following forum input? I don't think so.
Of course the act of ripping all that out is more delay.
Chip, is his own man of course. However he can't resist exploring interesting ideas...thank goodness.
But several people are blaming forum folks for the P2 problems. They need to stuff it.
I hold myself up as being in a very small part a contributor to that feed back loop. That loop lead to a design that was unworkable. And some would say wasted a year.
I'm very confident that things are on the right track now and that all Chip has learned will be used to good effect.
No, that's far too simplistics. I'd even say wrong. The Prop2 was on target as a beefy design long before that. Had the first shuttle run worked I think you would have seen a hot IC result from even that.
IMHO the hubexec has been the biggest and single most benefit to come out of all this reworking. This was discovered in a fairly innocent discussion last Thanksgiving. It did however, have a big impact on the design, but probably the P2 was over budget on power anyway.
Now, the new P1+/P2, has 512KB of hub (major plus), 16 cogs (simpler and leaner) (major plus), and Chip seems to be able to crank the speed up as a result (another plus, because we lost some speed from the original P2 design).
Some of you may not have realised, but much of the smart I/O was already there, just hidden from us in special instructions.
Since I do believe that, then yes, I guess I am "that out of touch".
I do not resile from any of the comments I have made. We could have had a workable P2 over a year ago. Now, it looks like we might have something that looks a lot like that chip again now. A year late.
Ross.
Not totally wrong though. Clearly in all those months of debate, wrangling, and feature accumulation we forgot to check if the thing was actually buildable.
Never mind. Thinks are on a good track now.
Thermal behaviour had never been check for irrespective of forum involvement. It's just one of the stepping stones is all. Associating this hiccup with the forum is wrong.
I sincerley hope it's only a "hiccup" in in time. But from here it looks like a major rearchitecting. The sort of thing that would give my boss and our backers heart failure.
I look forward to Chip writing a follow on story "Why the Propeller II works" with all the gory details of the trials and tribulations along the way and how the collaborative approach helped and/or hindered progress.
The P2 has been brewing for something like 8 years now, so the last year and a bit can't take the blame. It has only been what - two or three years - since the switch to verilog.
That was done.
Now, the process physics mandate a different approach. A ton was learned about how to design a killer chip in this process.
They still want a really competitive chip. The future, among other things, needs to be funded. Right now, Chip is maximizing what he learned so that the end result is as awesome as possible.
Yes, we have a feedback loop going on, and it's an important one because it helps trigger Chip's thinking in ways he would not have otherwise and that has been determined to be a good thing.
Relax, voice your opinion and let the process that has evolved here happen and we are going to get an awesome chip!
Personally, I agree with Roy. This design is looking great! The emphasis on features changed a little and for the better, again in this process physics.
Nobody should be blaming anyone.
Chip and Ken have mentioned over the years how Chip tends to work alone and when they saw the need for Chip to interact more, get some fuel for the mental fire he really needs to shine bright, they did that. What we say here is important. But it's not something we need blame ourselves for, because the simple truth is what we say here is also necessary.
Ask them. I'm right about this. Relax.