REPEAT P1 becomes P2 which becomes P1+ which becomes P1++
Peter Jakacki
Posts: 10,193
Oh no, besides the very confusing reference to the new design being called a P1+ when previously for many years any substantial upgrade of the P1 was going to be the P2 but that design was incrementally improved minute by minute day by day until it was nothing like a P2 although it was still called P2 and then P2 couldn't be fabricated as it was then so we have a "compromise" chip which is still far more than the original P2 but to be called a P1+ ???? and it is going through the same minute by minute incremental "improvements" until it becomes a P1++, an apt name since it seems to increment itself but still we have nothing hard and fast in terms of practical P2 silicon which btw is what the next substantially improved silicon should be referred to after the original P1 silicon from 2006.
It would not even be so bad if the forum members could spare some time from posting to actually collaborate and document as they suggest "improvements", but other than picking through hundreds or even thousands of posts there is no way to know what the current state of anything is. History is repeating itself, is repeating itself, is repeating itself.
Please just make the P2 that we've been waiting loyally for all these years and then all those bells and whistles and just-in-(someone's special)-case features can be tested and fabricated into silicon as a hopefully commercially viable P3. I would really really like to know that we will have P2 silicon in the form of P16X32B or whatever in 2014.
It would not even be so bad if the forum members could spare some time from posting to actually collaborate and document as they suggest "improvements", but other than picking through hundreds or even thousands of posts there is no way to know what the current state of anything is. History is repeating itself, is repeating itself, is repeating itself.
Please just make the P2 that we've been waiting loyally for all these years and then all those bells and whistles and just-in-(someone's special)-case features can be tested and fabricated into silicon as a hopefully commercially viable P3. I would really really like to know that we will have P2 silicon in the form of P16X32B or whatever in 2014.
Comments
So Chip is re-iterating, and seems to be quite well focused on staying in the P1+ region, in order to craft a device that can meet the power-envelope requirements.
It makes sense to include as much of P2, as practically does stay inside the power envelope.
Next step will be a FPGA test version, and then a OnSemi Sim run should confirm Power Envelope and die area targets.
As more has moved to the OnSemi flows, that side of things looks to be more controlled.
Because the P2 is there as a FPGA proven reference, much of this is moving a lot faster than 'greenfields' development.
The "P1+", so called because it's not quite the old P2, is actually now the P2.
The P3, formerly "P2", will of course never exist because whenever the P2 hits the silicon lessons will have been learned, priorities and requirements changed and a new P3 plan will emerge.
All pretty straight forward:)
Some number of people complain that the new product should be given the name P2.
I disagree. The P2 had a shuttle run last year, which failed.
It was tweaked to hell and back, and then failed to be manufacturable via OnSemi, at least realistically for the space.
There is also a fair amount of Parallax-Semi "P2" PR thats been published that just isn't compatible with the current product.
So, naming this product the P2 will always bring up comments here and elsewhere that show it as a different product (the failed ones), etc.
The P2 failed.
Call this the P3 or something else, and avoid forcing customers to deal with all of these hassles and potential confusion.
Nobody in the real world is going to give 2 sh*** about whether its called P2/P3/P4, except for bad Intel dejavu.
People in the forums already know the deal. So aside from some anal desire for 'having to have' a "P2", just make the confusion go away with a name that doesn't engender wasted brain time, and baggage?
Makes no sense to call it P3 instead of P2. It should either be P2 or something new, but I would go with calling it Propeller 2.
Most of Parallax's customers don't read the forums or go to the Expos, and so they wouldn't even know about the P2 trials and tribulations beyond maybe the info on the main parallax site, aka the early specs page, if that.
Right now, it looks like a repeat only because all that was learned is being picked through, pruned to account for the process physics, and factored into the more P1 like design, which keeps a much simpler basic operation as primary.
Things like "smart pins" take advantage of pretty great I/O hardware that really should get used.
So it looks like a repeat, but it's not gonna be. Just a rapid step through what we've got, selection of the possible, and some engineering needed to connect and make use of the bits we know rock.
Perhaps a shared spreadsheet or wiki would have a chance of keeping up. I think Dave Hein had a whats in/out summary.
Just had another look at the unofficial P2 document. I think we should wait for Chip to release the next DE0 image, and docs before working out what to do there
The P2 published spec on Parallax Semi is for 8x200 1600 mips, 1080p/cog, etc.
It failed.
The next chip being designed is logically the P3.
Yes, there is also a logic that we can try to hide all that and just do a quick change of the published specs and assume no one will notice or care.
And then assuming this does go on to more successful than the Prop, having all these threads pop up on searches will continually have to be replied to as 'oh, that's the old P2 design'...
And of course any decent review of the new product will in fact probably find the original P2 specs, these threads, and could imply that Parallax failed with the 'Real P2' and had to drop theor sights and come out with a lesser chip. Is it good to have a piece indicate your part is some sort of Plan B, because R&D couldn't make good after x years on Plan A?
Because you know some writers are just going to be looking for some way to dismiss Parallax in favor of their ARM/PIC/Addition bias.
Why give them the ammo to take you down with?
Some may pooh-pooh this, and I'm not saying it would be the end of the world.
However, why take the risk?
Keep P2 as the internal name maybe, and something more useful and descriptive and attention grabbing for the public and news sites/copy writers...P16?
Maybe it should be the SweetPea..........
I don't really care what it is called as long as the specs demonstrate a big boost in resources. And we seem to be on track for that with 16 cogs, 512Kb of RAM, 64 ADC/DAC, and a bunch of other features that are too geeky for me to follow through development.
I guess the Beanie logo is going as not acceptable by corporate 'suits'. So the 'powers that be' could call it a P38 Lightning for good measure... I just wanna buy a few.
http://en.wikipedia.org/wiki/P-38_Lightning
Well, names do matter, witness Chevy and the NOVA in Spanish......
Also, why some arcane airplane descriptor which isn't any better than a car analogy.
At least P16 is a clear reference to 16 cores, not to mention the M16.
Besides the technical features which will impact the product's ability to pique interest, the name should, and will also.
P2 is generic, non-informative, and has potential baggage.
Would love to see what Ken thinks. No real sense in making a long thread full of angst either
These questionsand many otherswill be answered in the next episode of...Soap.
As for the internal reference let's not get ourselves confused, so names are important. The next silicon to be produced will be a vast improvement on P1 so therefore that is what we would call P2 internally. Just because P2 was being enhanced each day beyond the specs of the failed shuttle runs doesn't mean we are locked into calling that a P2. As I have stated before this enhanced P2 should logically be called P3 but as we know it is not viable in it's current form anyway. Looking back over the years (sigh) at pdfs and posts regarding P2 it is plain to see that this P16X32B is far more than the original P2 before it was morphed into P3, so what's the problem?
Parallax Semiconductor website never ever kept up to date with the way the P2 design was morphing into P3 so it's not like any customer had any hard and fast idea of what P2 would eventually be like, except that it would be so much better than P1. Of course the labels P1, P2, and P3 are mainly for us forumistas so that we know what we are talking about as Parallax will label the chip anything they like.
So maybe to avoid any confusion we just say P2 for whatever makes it into production and P3 for the uberProp which may end up being manufactured in 65nm but if we wait long enough we might end up in 22nm and maybe even 5nm (some Aussies made a 7 atom transistor).
sure. But it is upside down. Like this forth stuff you will have running as soon as you get any real chips...
Enjoy!
Mike