A Proposal for Resolving the P2 Power Issue

Dave Hein

If you look at the P2 Spec at http://www.parallaxsemiconductor.com/Products/propeller2specs you will see that the P2 had the following features:

P1 Core
4-port cog memory
20-bit multiplier
126K RAM
2K ROM
32-bit Multiply/Divide
Cordic Engine
PTRA/PTRB
INDA/INDB
256-long CLUT/FIFO
PTRX/PTRY
Data Cache
265 Instructions
128-bit Hub Bus

I think this spec was posted about 2 years ago. Since then, Chip realized that if he got rid of the huge bus supporting ADCs for every pin he could add more hub RAM, which is probably a good thing. However, it then opened the flood gate for lots of new features, which consume real estate and require power. The major new features that were added were:

256-bit Hub Bus
4 tasks
128K More Hub RAM
hubex
4 Instruction Caches
serial I/O
Pre-emptive threads
100+ Special Instructions

There are various proposals to go back to the P1, and add some features to make it a more useful chip. I think this is the wrong approach. I propose to Parallax that they go back to the P2 at the point when the big bus was removed and the number of ADCs was reduced, but before the extra 128K of RAM was added. Evaluate the power requirements of that chip, and determine if it is doable at 180nm.

If the earlier design for the P2 is doable then some of the other features could be considered for addition if they still allow the chip to meet the power goals.

This approach allows Parallax to move forward with the P2 design rather than regressing back to the P1 and adding features to it.

pedward

Correction, after the DAC bus was trimmed, the features added were:

More RAM
WIDE RAM bus
ICACHE x 4
Pre-emptive task switching
More instruction customization

I might be wrong, but believe that hubex 1.0 was available prior to the DAC bus removal. Single threaded hubex wasn't a huge complexity adder, it was the 4 256bit wide cache lines that added 9000 flip-flops or transistors (can't recall) to each COG.

cgracey

Even back then, the P2 was way more complicated than what we have the power budget for now, in light of recent simulations by OnSemi. We need to drastically reduce the complexity. Going back to Prop1 is a good starting point.

Dave Hein

pedward and Chip, thanks for your responses. I guess the decision has already been made to do a P1+ chip instead of the P2.