Consensus on the P16X32B?
RossH
Posts: 5,462
UPDATE: Chip has started a new thread on this chip here.
All,
In this thread about the P2, Chip proposed a new chip, tentatively called the P16X32B:
So, what about this:
100 pin 14x14mm exposed thermal pad TQFP package (Tja=20) with internal down-bonds to GND, so no pins needed for GND
16 x 1.8V VDD pins, at four per side, with internal down-bonds for GND
XI, XO, RESn, BOEn pins
64 I/O pins with a unique 3.3V VDD pin for every 4 pins (and internal down-bond for GND) - this is important for analog and high-speed switching
(that makes 100 pins, not including 32 internal down-bonds for GND)
16 two-clocks-per-instruction Prop1 cogs
256KB hub RAM with simple round-robin cog access - this maintains the same 8:1 instruction:hub-cycle ratio as the current Prop1
200MHz clock - cogs run at 100 MIPS, CTRs at 200 MHz
1600 total MIPS - 10x faster than current Prop1 chip
Center of die is only 4.3 x 4.3mm. Die is 5.4 x 5.4mm with pad frame, or 29.16 square mm (54% of current projected Prop2 die size)
This chip could be called P16X32B, as per current convention.
Manufacturing cost would be ~$1.90, assuming $950/wafer, 950 die per wafer, 80% yield, $0.50 per package, $0.15 total testing. 1K piece price would be ~$6.00.
This chip would behave like Prop1 with twice the cogs, all running 5x faster, and with 8x the hub RAM, plus 2x the I/O pins with new analog capabilities.
This would be really easy to make happen and the chance of latent bugs would be very low.
A little later, Chip posted about another chip, which I will call the P32X32B:
This would be a very simple chip to complete. It would be kind of a relief, for now.
Prop2 still needs a serdes and some thorough testing. I'd hate to have another false start.
I could see making a 32-cog 3200 MIPS Prop1 w/64 analog I/Os and 512KB RAM for now and then continue to get Prop2 ready for a smaller process.
If I felt some consensus here about doing that, it would be pretty easy to attack that project in short order.
These posts define an envelope for a P1 variant that Chip believes would be quick and easy to achieve.
Since that thread is dedicated to the P2, and this new proposal is not intended to either replace or derail the current P2, I thought I'd start another thread specifically to gauge the level of consensus for a P16X32B, a P32X32B or some other P1 variant within the same envelope.
This is not a thread about the features of such a chip, or bewailing the current state of the P2 development, or complaining that this new chip might undermine the P2 - any further discussion on these subjects should continue in the original thread. But I also decided not to make this a simple "poll", thread since I do expect and want more than just a "+1" response, and I think most forum members will not abuse that opportunity.
In this thread, please just let Chip know if you want to see a variant within the envelope Chip has said would be quick and easy to achieve, and also whether you would be willing to fund its development (should Parallax choose to use some kind of non-equity based crowd-funding model). If you are against it, by all means say so. Just try to keep it brief in either case. In summary:
If you want a variant within this envelope, vote Yes, and indicate if you would be willing to assist in funding it.
If you don't want to see a variant within this envelope, vote No.
Just to get things rolling, and to avoid any doubt, here are my answers:
Yes I want it, and Yes I would be willing to help fund it.
Let the games begin!
Ross.
Running tally (up to post #267) **
For:
- RossH (and will fund)
- David Betz (and will fund)
- dr hydra
- jazzed
- Roy Eltham (and will fund)
- Peter Jakacki
- mindrobots (and will fund)
- Bob Lawrence (VE1RLL)
- kwinn
- william chan
- Lawson (and may fund)
- Cluso99 (and will fund, preference for P32X32)
- ospropdev
- AntoineDoinel
- W9GFO
- msrobots
- Ken Gracey (and will inherently fund!)
- Ramon (and will fund)
- Roger Lee
- Brian Fairchild (and will fund)
- Baggers (and will fund)
- rjo__
- John Abshier (and will fund)
- 4x5n
- FredBlais (and will fund)
- LeoD (and will fund)
- pgbpsu
- tomcrawford
- Mickster (and will fund)
- KMyers
- Electrodude
- Publison (and will fund)
- base2design (and will fund)
- dnalor
- hippy
- Gordon McComb
- Invvebt0O-Doc (and will fund)
- JRetSapDoog (and will fund)
- NWCCTV
- Coley
- localroger
- Tracey Allen (and will fund)
- altosack
- T Chap (and will fund)
- Dr_Acula
- koehler
- pik33
- Heater.
- Dave Hein
- Bill Henning
- rogloh
- Kerry S
** If anyone feels I have misrepresented their position, just let me know!
Comments
Can I vote more than once?
Only if you intend voting Yes.
I'm all for a bigger HUB RAM, and more COGs etc... before P2 comes.
But, for which chip do you want consensus? There are 2 described in the opening post.
In the other thread I suggested a 64 entry vector, of five bit fielts, indexed by a 6 bit counter running from the 200Mhz clock for assigning hub cycles.
Default would be 0-31,0-31 (cogid) for who gets the slot, but it could be re-programmed for deterministic timing at whatever grain needed.
EDIT: Some would like this P2 to be enhanced as well but it is already a thumping roaring beast, don't complicate this design, leave the all-nighters and trials and errors for the P3.
I guess the answer is it would be derived from the current P2 rather than any part of original P1.
True. It was originally about the first one (the P16X32B). But I would also vote in favor of the second one. I'll update the first post to clarify.
Ross.
Chip, you are the Chief Visionary and Chief Technical Officer.
Ken you are the Chief Bean Counter (no offense intended) and Chief Business Realist.
Between the two of you the future will be decided - INCLUDING THE DESIGN AND FEATURES of ANY chip.
If there is to be a PaaXbb chip, and a mob funding program, I will support it with whatever cash I have ldftover from buying two Nanos and a DE2 for Prop2 testing. I'll also volunteer time and skills as able and needed.
I'm dead serious. If you don't say where you're going, you will never get there.
Sounds great to me. I vote yes.
Re:P2 @chip
We really don't have enough features for the prop2 yet anyway LOL
Thanks! People value your opinion! I'm starting to feel like Rodney Dangerfield around here!
Many different variants have been proposed.
eg
Agreed, but I would tweak to add a 'No-COG' mapping for power envelope control
- Power will still be an important issue on this device.
I would also expand the RAM x2, and reduce the COGs a little, especially if the device wants to target the large LCD driver business.
Needed here is a P1E COG to memory equivalent figure.
Other things should be lifted from P2, like Timers, and HubExec (non threaded) , and I think a device playing in the LCD area needs QuadSPI in silicon, to allow high bandwidth/low power FLASH access, and allow other micros, to access this as a slave.
Chip has compiling a 2 Clock, Dual Port design of the P1.
I think the P2 Peripheral ADC/DAC/Pins, are implicit in this P1E.
+1
To be perfectly honest everything I have done so far has been so simple that the P1 is overkill, but I have used the P1 for it's potential expandability, ease of use, and the help available from Parallax and this forum. There is only one project I would like to tackle that needs more than the P1 provides and the P16X32B exceeds that by a large margin.
Of course it is possible to vote. Chip has defined an envelope in which he believes he could easily and quickly develop some kind of P1 variant (i.e. a P1 with more pins, more Hub RAM and more speed). Before we get bogged down on specifics, let's see if we can achieve a consensus on whether we want such a variant.
If you want a variant within this envelope, vote yes.
If you don't want to see a variant within this envelope, vote no.
I personally don't believe there is any point in arguing about the detailed specifications of the variant (look where that has gotten us so far!) and am willing to leave these up to Parallax.
Ross.
Maybe that is the poll?
Chip has indicated this would be ~ $6, and the reference device I am thinking of is the SSD1963, which looks ~ $5 - but that SSD1963, is basically 'a memory playback' device, with a parallel host interface of moderate speed.
It lacks even Colour-table compression, and has no fonts.
A correctly scaled P1E can swallow all of a SSD1963, and easily add Fonts/Icons and Colour-table compression, and use a serial interface to the host device.
FTDI have an EVE video device, but that has much lower memory, so cannot compete on the same sized LCDs.
FTDI are making the market aware of Smarter LCD Drivers, which would help Parallax.
Marty
I don't think a poll gives quite enough scope for discussion, but I've updated the first post to reflect this is the intent.
Ross.
I am willing to help funding and think we would be better to do it via the forum and direct to Parallax (no 10% commission).
Perhaps a possible way would be for us to buy chip(s) from the shuttle run and pay up front. Whether they work or not its our problem and not Parallax's.
Perhaps $100 / chip ??? I know this does not cover the shuttle run, but if Parallax sold 100 then that is $10K. Might make for a decent quantity to be made on the first shuttle, and if they work we have working chips early. Obviously we need Ken's input, but this is a starting point.
BTW I agree with Bill's 32 hub slot mechanism - easy to describe, fairly simple to implement (I think).
I'd need a chip on a minimal dev board. A chip by itself does me no good. But I'm sure deals can be struck!
@Rick if the past is any indicator the forum could have 100 new board designs for you pretty quick. ;-)