communication protocol to get data from external uC to Prop !
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Until the Prop II is available, I have run out of capacity using the Prop I. I need to use the Prop I for bit-banging a non-standard protocol output (not my choice, but determined by another manufacturer). I'll be using a BeagleBone Black (BBB) as the master to provide the data.
Current question: what is the best way to get >4Mbps average data rate to the Prop (slave)? The data will be "lumpy", being driven by the BBB, so the maximum data rate may be as high as 10Mbps. If I can use an existing protocol (e.g. FTDI chip supporting USB) that's great. I have no desire to re-invent the wheel. If there is nothing standard that will support this data rate, I'm thinking of using something like a combination of SPI and I2C. If I use clock stretching (as in I2C) with an SPI protocol, I can have the master (BBB) clock data out, pulling a clock line (with weak pull-down) high whenever a new data word is read, then releasing it and polling for the clock line to be low before sending the next data. This will allow the Prop (slave) to "stretch" the clock by driving it high until ready for the next data, as in I2C. Does this make sense? Thanks.
Thinking about this some more, I guess this isn't really anything like SPI, it's pretty much a simple I2C, perhaps with multiple SDA lines for increased data rate.
Current question: what is the best way to get >4Mbps average data rate to the Prop (slave)? The data will be "lumpy", being driven by the BBB, so the maximum data rate may be as high as 10Mbps. If I can use an existing protocol (e.g. FTDI chip supporting USB) that's great. I have no desire to re-invent the wheel. If there is nothing standard that will support this data rate, I'm thinking of using something like a combination of SPI and I2C. If I use clock stretching (as in I2C) with an SPI protocol, I can have the master (BBB) clock data out, pulling a clock line (with weak pull-down) high whenever a new data word is read, then releasing it and polling for the clock line to be low before sending the next data. This will allow the Prop (slave) to "stretch" the clock by driving it high until ready for the next data, as in I2C. Does this make sense? Thanks.
Thinking about this some more, I guess this isn't really anything like SPI, it's pretty much a simple I2C, perhaps with multiple SDA lines for increased data rate.
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Looked again, and I did find the 10Mbaud you mentioned here: http://obex.parallax.com/object/230
The challenge (I think) may be differences in clock speed between master and slave. Maybe better said as "clock accuracy" rather than clock speed. The two devices have very different clock speeds, but will I be able to reliably synchronize the two clocks?
Thanks.